x = a | b
	c16 := uint32(0x0000ffff)
	a = x >> 16 & c16
	b = (x & c16) << 16
	x = a | b
	return x
}

// Prefetch prefetches data from memory addr to cache
//
// AMD64: Produce PREFETCHT0 instruction
//
// ARM64: Produce PRFM instruction with PLDL1KEEP option
func Prefetch(addr uintptr) {}

// PrefetchStreamed prefetches data from memory addr, with a hint that this data is being streamed.

	"PMULLW",
	"PMULULQ",
	"POPAL",
	"POPAW",
	"POPCNTL",
	"POPCNTQ",
	"POPCNTW",
	"POPFL",
	"POPFQ",
	"POPFW",
	"POPL",
	"POPQ",
	"POPW",
	"POR",
	"PREFETCHNTA",
	"PREFETCHT0",
	"PREFETCHT1",
	"PREFETCHT2",
	"PSADBW",
	"PSHUFB",
	"PSHUFD",
	"PSHUFHW",
	"PSHUFL",
	"PSHUFLW",
	"PSHUFW",
	"PSIGNB",
	"PSIGND",
	"PSIGNW",
	"PSLLL",
	"PSLLO",

			prefix = "qword "
		case LAR:
			prefix = "word "
		case BOUND:
			if inst.Mode == 32 {
				prefix = "qword "
			} else {
				prefix = "dword "
			}
		case PREFETCHW, PREFETCHNTA, PREFETCHT0, PREFETCHT1, PREFETCHT2, CLFLUSH:
			prefix = "zmmword "
		}
		switch inst.Op {

		// Prefetch instructions
		// Do prefetch arg0 address. arg0=addr, arg1=memory. Instruction variant selects locality hint
		{name: "PrefetchT0", argLength: 2, reg: prefreg, asm: "PREFETCHT0", hasSideEffects: true},
		{name: "PrefetchNTA", argLength: 2, reg: prefreg, asm: "PREFETCHNTA", hasSideEffects: true},

		// CPUID feature: BMI1.

	POPAD:           "POPAD",
	POPCNT:          "POPCNT",
	POPF:            "POPF",
	POPFD:           "POPFD",
	POPFQ:           "POPFQ",
	POR:             "POR",
	PREFETCHNTA:     "PREFETCHNTA",
	PREFETCHT0:      "PREFETCHT0",
	PREFETCHT1:      "PREFETCHT1",
	PREFETCHT2:      "PREFETCHT2",
	PREFETCHW:       "PREFETCHW",
	PSADBW:          "PSADBW",
	PSHUFB:          "PSHUFB",
	PSHUFD:          "PSHUFD",

	&& isSameCall(sym, "runtime.memmove")
	&& call.Uses == 1
	&& isInlinableMemmove(dst, src, sz, config)
	&& clobber(call)
	=> (Move [sz] dst src mem)

// Prefetch instructions
(PrefetchCache ...)   => (PrefetchT0 ...)
(PrefetchCacheStreamed ...) => (PrefetchNTA ...)

// CPUID feature: BMI1.
(AND(Q|L) x (NOT(Q|L) y))               && buildcfg.GOAMD64 >= 3 => (ANDN(Q|L) x y)

	POR X11, X11                            // 66450febdb
	PREFETCHNTA (BX)                        // 0f1803
	PREFETCHNTA (R11)                       // 410f1803
	PREFETCHT0 (BX)                         // 0f180b
	PREFETCHT0 (R11)                        // 410f180b
	PREFETCHT1 (BX)                         // 0f1813
	PREFETCHT1 (R11)                        // 410f1813
	PREFETCHT2 (BX)                         // 0f181b

				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "PrefetchT0",
		argLen:         2,
		hasSideEffects: true,
		asm:            x86.APREFETCHT0,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB