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Results 1 - 5 of 5 for PSLLL (0.03 sec)
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src/internal/chacha8rand/chacha8_amd64.s
#define QR(A, B, C, D, T) \ PADDD B, A; PXOR A, D; ROL16(D, T); \ PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $12, T; PSRLL $20, B; PXOR T, B; \ PADDD B, A; PXOR A, D; ROL8(D, T); \ PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $7, T; PSRLL $25, B; PXOR T, B // REPLREG replicates the register R into 4 uint32s in XR. #define REPLREG(R, XR) \ MOVQ R, XR; \ PSHUFD $0, XR, XR
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Dec 05 20:34:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/cmd/internal/obj/x86/anames.go
"PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFL", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLL", "PSLLO", "PSLLQ", "PSLLW", "PSRAL", "PSRAW", "PSRLL", "PSRLO", "PSRLQ", "PSRLW", "PSUBB", "PSUBL", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
PSLLL $7, M2 // 0f72f207 PSLLL $7, M3 // 0f72f307 PSLLL (BX), X2 // 660ff213 PSLLL (R11), X2 // 66410ff213 PSLLL X2, X2 // 660ff2d2 PSLLL X11, X2 // 66410ff2d3 PSLLL (BX), X11 // 66440ff21b
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/crypto/aes/gcm_amd64.s
MOVOU (16*14)(KS), T0 initEncLast: AESENCLAST T0, B0 PSHUFB BSWAP, B0 // H * 2 PSHUFD $0xff, B0, T0 MOVOU B0, T1 PSRAL $31, T0 PAND POLY, T0 PSRLL $31, T1 PSLLDQ $4, T1 PSLLL $1, B0 PXOR T0, B0 PXOR T1, B0 // Karatsuba pre-computations MOVOU B0, (16*14)(dst) PSHUFD $78, B0, B1 PXOR B0, B1 MOVOU B1, (16*15)(dst) MOVOU B0, B2 MOVOU B1, B3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 23.4K bytes - Viewed (0) -
src/vendor/golang.org/x/crypto/chacha20poly1305/chacha20poly1305_amd64.s
#else #define ROL8(R, T) ROL(8, R, T) #endif #define chachaQR(A, B, C, D, T) \ PADDD B, A; PXOR A, D; ROL16(D, T) \ PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $12, T; PSRLL $20, B; PXOR T, B \ PADDD B, A; PXOR A, D; ROL8(D, T) \ PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $7, T; PSRLL $25, B; PXOR T, B #define chachaQR_AVX2(A, B, C, D, T) \ VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol16<>(SB), D, D \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 21:28:33 UTC 2023 - 105.6K bytes - Viewed (0)