{name: "SRL", argLength: 2, reg: gp21, asm: "LSR"},                        // arg0 >> arg1, unsigned, shift amount is mod 64
		{name: "SRLconst", argLength: 1, reg: gp11, asm: "LSR", aux: "Int64"},     // arg0 >> auxInt, unsigned, auxInt should be in the range 0 to 63.

	AESE	V30.B16, V7.B16
	AESMC	V7.B16, V7.B16
	ADD	R0, R2, R10
	SUB	$128, R10, R10
	VLD1.P	64(R10), [V8.B16, V9.B16, V10.B16, V11.B16]
	VLD1	(R10), [V12.B16, V13.B16, V14.B16, V15.B16]
	SUB	$1, R2, R2
	LSR	$7, R2, R2

aesloop:
	AESE	V8.B16,	 V0.B16
	AESMC	V0.B16,  V0.B16
	AESE	V9.B16,	 V1.B16
	AESMC	V1.B16,  V1.B16
	AESE	V10.B16, V2.B16
	AESMC	V2.B16,  V2.B16
	AESE	V11.B16, V3.B16

	if is_w {
		rsa.reg = W0 + Reg((x>>16)&(1<<5-1))
	} else {
		rsa.reg = X0 + Reg((x>>16)&(1<<5-1))
	}
	switch (x >> 22) & 0x3 {
	case 0:
		rsa.extShift = lsl
	case 1:
		rsa.extShift = lsr
	case 2:
		rsa.extShift = asr
	case 3:
		if has_ror {
			rsa.extShift = ror
		} else {
			return nil
		}
	}
	rsa.show_zero = true
	rsa.amount = uint8((x >> 10) & (1<<6 - 1))