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Results 11 - 20 of 43 for vsraw (0.04 sec)
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src/math/asinh_s390x.s
BYTE $0xFF LGDR F0, R5 SRAD $32, R5 MOVH $0x0, R2 SUBW R5, R3 FMOVD $0, F8 RISBGZ $32, $47, $0, R3, R4 BYTE $0x18 //lr %r1,%r4 BYTE $0x14 RISBGN $0, $31, $32, R4, R2 SUBW $0x100000, R1 SRAW $8, R1, R1 ORW $0x45000000, R1 BR L6 L2: MOVD $0x30000000, R2 CMPW R1, R2 BGT L16 FMOVD 200(R9), F2 FMADD F2, F0, F0 L1: FMOVD F0, ret+8(FP) RET L14: LTDBR F0, F0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 5.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
PSRAW $7, M2 // 0f71e207 PSRAW $7, M3 // 0f71e307 PSRAW (BX), X2 // 660fe113 PSRAW (R11), X2 // 66410fe113 PSRAW X2, X2 // 660fe1d2 PSRAW X11, X2 // 66410fe1d3 PSRAW (BX), X11 // 66440fe11b
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
build-logic/kotlin-dsl-shared-runtime/src/main/kotlin/org/gradle/kotlin/dsl/internal/sharedruntime/codegen/ApiExtensionsGenerator.kt
listOf(targetType.sourceName, name) + parameters.flatMap { apiTypeKey(it.type) } } private fun apiTypeKey(usage: ApiTypeUsage): List<Any> = usage.run { listOf(sourceName, isNullable, isRaw, variance) + typeArguments.flatMap(::apiTypeKey) + bounds.flatMap(::apiTypeKey) } // TODO Policy for extensions with reified generics // // Goals // - make the dsl predictable
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Dec 20 21:41:53 UTC 2023 - 18.1K bytes - Viewed (0) -
test/codegen/shift.go
return v >> (s & 31) } func rshMask32x64(v int32, s uint64) int32 { // arm64:"ASR",-"AND" // ppc64x:"ISEL",-"ORN" // riscv64:"SRAW","OR","SLTIU" // s390x:-"RISBGZ",-"AND",-"LOCGR" return v >> (s & 63) } func rsh5Mask32x64(v int32, s uint64) int32 { // riscv64:"SRAW",-"OR",-"SLTIU" return v >> (s & 31) } func lshMask64x32(v int64, s uint32) int64 { // arm64:"LSL",-"AND"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/math/log10_s390x.s
RISBGZ $40, $55, $56, R3, R2 RISBGZ $57, $60, $51, R3, R3 ORW $0x45000000, R2 BR L4 L13: BGE L18 //jnl .L18 BVS L18 FMOVD log10rodataL19<>+16(SB), F0 BR L1 L17: SRAW $1, R2, R2 SUBW $0x40000000, R2 BR L8 L18: FMOVD log10rodataL19<>+8(SB), F0 WORD $0xED009000 //ddb %f0,.L36-.L19(%r9) BYTE $0x00 BYTE $0x1D
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 4.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y) (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y) (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVHreg x) y) (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVBreg x) y) // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. // result = shift >= 64 ? 0 : arg << shift
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/math/atanh_s390x.s
WORD $0xED305088 //sdb %f3,.L12-.L10(%r5) BYTE $0x00 BYTE $0x1B SUBW R4, R2 WFSDB V3, V2, V3 RISBGZ $32, $47, $0, R2, R1 SLD $32, R1, R1 LDGR R1, F2 WFMADB V4, V2, V16, V4 SRAW $8, R2, R1 WFMADB V4, V5, V6, V5 WFMDB V4, V4, V6 WFMADB V4, V1, V7, V1 WFMADB V2, V3, V4, V2 WFMADB V1, V6, V5, V1 FMOVD 56(R5), F3 FMOVD 48(R5), F5 WFMADB V4, V5, V3, V4
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 5.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
SLD $4, R3, R6 // eb630004000d SLD R2, R3, R6 // eb632000000d SRAD $4, R5, R8 // eb850004000a SRAD R3, R5, R8 // eb853000000a SRAW $4, R5, R8 // eb85000400dc SRAW R3, R5, R8 // eb85300000dc RLL R1, R2, R3 // eb321000001d RLL $4, R2, R3 // eb320004001d RLLG R1, R2, R3 // eb321000001c
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0)