Search Options

Results per page
Sort
Preferred Languages
Advance

Results 11 - 20 of 65 for mulld (0.08 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64.s

    	MULLW R3, R4                    // 7c8419d6
    	MULLW R3, R4, R5                // 7ca419d6
    	MULLW $10, R3                   // 1c63000a
    	MULLW $10000000, R3             // 641f009863ff96807c7f19d6
    
    	MULLWCC R3, R4, R5              // 7ca419d7
    	MULHW R3, R4, R5                // 7ca41896
    
    	MULHWU R3, R4, R5               // 7ca41816
    	MULLD R3, R4                    // 7c8419d2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  2. test/codegen/mathbits.go

    func Mul(x, y uint) (hi, lo uint) {
    	// amd64:"MULQ"
    	// arm64:"UMULH","MUL"
    	// ppc64x:"MULHDU","MULLD"
    	// s390x:"MLGR"
    	// mips64: "MULVU"
    	// riscv64:"MULHU","MUL"
    	return bits.Mul(x, y)
    }
    
    func Mul64(x, y uint64) (hi, lo uint64) {
    	// amd64:"MULQ"
    	// arm64:"UMULH","MUL"
    	// ppc64x:"MULHDU","MULLD"
    	// s390x:"MLGR"
    	// mips64: "MULVU"
    	// riscv64:"MULHU","MUL"
    	return bits.Mul64(x, y)
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/S390X.rules

    // TODO(mundaym): indexed versions of these?
    ((ADD|SUB|MULLD|AND|OR|XOR) <t> x g:(MOVDload [off] {sym} ptr mem))
      && ptr.Op != OpSB
      && is20Bit(int64(off))
      && canMergeLoadClobber(v, g, x)
      && clobber(g)
      => ((ADD|SUB|MULLD|AND|OR|XOR)load <t> [off] {sym} x ptr mem)
    ((ADD|SUB|MULL|AND|OR|XOR)W <t> x g:(MOVWload [off] {sym} ptr mem))
      && ptr.Op != OpSB
      && is20Bit(int64(off))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/S390XOps.go

    		{name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true},                                // arg0 * arg1
    		{name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true, resultInArg0: true, clobberFlags: true},                                // arg0 * arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 52.5K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
    (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
    (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
    (Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
    (Mod32 x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVW x y)))
    (Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)
    (Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true}, // arg0*arg1 (signed 64-bit)
    		{name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true}, // arg0*arg1 (signed 32-bit)
    		{name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int32", typ: "Int64"}, // arg0*auxInt (signed 64-bit)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/arm/anames.go

    	"MOVWF",
    	"MOVDW",
    	"MOVFW",
    	"MOVFD",
    	"MOVDF",
    	"MOVF",
    	"MOVD",
    	"CMPF",
    	"CMPD",
    	"ADDF",
    	"ADDD",
    	"SUBF",
    	"SUBD",
    	"MULF",
    	"MULD",
    	"NMULF",
    	"NMULD",
    	"MULAF",
    	"MULAD",
    	"NMULAF",
    	"NMULAD",
    	"MULSF",
    	"MULSD",
    	"NMULSF",
    	"NMULSD",
    	"FMULAF",
    	"FMULAD",
    	"FNMULAF",
    	"FNMULAD",
    	"FMULSF",
    	"FMULSD",
    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  8. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	MTMSRD:         "mtmsrd",
    	MULHD:          "mulhd",
    	MULHDCC:        "mulhd.",
    	MULHDU:         "mulhdu",
    	MULHDUCC:       "mulhdu.",
    	MULHW:          "mulhw",
    	MULHWCC:        "mulhw.",
    	MULHWU:         "mulhwu",
    	MULHWUCC:       "mulhwu.",
    	MULLD:          "mulld",
    	MULLDCC:        "mulld.",
    	MULLDO:         "mulldo",
    	MULLDOCC:       "mulldo.",
    	RFID:           "rfid",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/armv6.s

    	MULF	F0, F1, F2    // 002a21ee
    	MULD.EQ	F3, F4, F5    // 035b240e
    	MULF.NE	F0, F2        // 002a221e
    	MULD	F3, F5        // 035b25ee
    	NMULF	F0, F1, F2    // 402a21ee
    	NMULF	F3, F7        // 437a27ee
    	NMULD	F0, F1, F2    // 402b21ee
    	NMULD	F3, F7        // 437b27ee
    	MULAF	F5, F6, F7    // 057a06ee
    	MULAD	F5, F6, F7    // 057b06ee
    	MULSF	F5, F6, F7    // 457a06ee
    	MULSD	F5, F6, F7    // 457b06ee
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Dec 21 16:30:51 UTC 2017
    - 4.6K bytes
    - Viewed (0)
  10. test/codegen/floats.go

    func Mul2(f float64) float64 {
    	// 386/sse2:"ADDSD",-"MULSD"
    	// amd64:"ADDSD",-"MULSD"
    	// arm/7:"ADDD",-"MULD"
    	// arm64:"FADDD",-"FMULD"
    	// ppc64x:"FADD",-"FMUL"
    	// riscv64:"FADDD",-"FMULD"
    	return f * 2.0
    }
    
    func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIV"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
Back to top