{name: "SUBFCconst", argLength: 1, reg: gp11cxer, asm: "SUBC", aux: "Int64"},                       // auxInt - arg0 (carry is ignored)
		{name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB"},                                               // arg0-arg1
		{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"},                                             // arg0-arg1

		// Note, the FPU works with float64 in register.

		{name: "FSUBS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FSUBS", resultInArg0: true},                    // fp32 arg0 - arg1
		{name: "FSUB", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FSUB", resultInArg0: true},                      // fp64 arg0 - arg1

		{name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true},   // arg0 + arg1
		{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"},                      // arg0 - arg1
		{name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD"},                      // arg0 - arg1
		{name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true},   // arg0 * arg1

(FADDD a (FMULD  x y)) && a.Block.Func.useFMA(v) => (FMADDD  a x y)
(FSUBS a (FMULS  x y)) && a.Block.Func.useFMA(v) => (FMSUBS  a x y)
(FSUBD a (FMULD  x y)) && a.Block.Func.useFMA(v) => (FMSUBD  a x y)
(FSUBS (FMULS  x y) a) && a.Block.Func.useFMA(v) => (FNMSUBS a x y)
(FSUBD (FMULD  x y) a) && a.Block.Func.useFMA(v) => (FNMSUBD a x y)
(FADDS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMSUBS  a x y)

	SUBSW R2.SXTH<<3, R13, R6                  // a6ad226b
	SUBS R21.UXTX<<2, R27, R4                  // 646b35eb
	SUBSW $(44<<12), R6, R9                    // SUBSW $180224, R6, R9         // c9b04071
	SUBS $(1804<<12), R13, R9                  // SUBS $7389184, R13, R9        // a9315cf1
	SUBSW R22->28, R6, R7                      // c770966b
	SUBSW R22>>28, R6, R7                      // c770566b
	SUBS R26<<15, R6, R16                      // d03c1aeb

(Select0 (F(ADDS|SUBS) (FMULS y z) x)) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)

// Convert floating point comparisons against zero into 'load and test' instructions.
(F(CMP|CMPS) x (FMOV(D|S)const [0.0])) => (LT(D|E)BR x)
(F(CMP|CMPS) (FMOV(D|S)const [0.0]) x) => (InvertFlags (LT(D|E)BR <v.Type> x))

// FSUB, FSUBS, FADD, FADDS now produce a condition code representing the

	FRSQRTE:        "frsqrte",
	FRSQRTECC:      "frsqrte.",
	FSEL:           "fsel",
	FSELCC:         "fsel.",
	FSQRTS:         "fsqrts",
	FSQRTSCC:       "fsqrts.",
	FSUBS:          "fsubs",
	FSUBSCC:        "fsubs.",
	ICBI:           "icbi",
	LD:             "ld",
	LDARX:          "ldarx",
	LDU:            "ldu",
	LDUX:           "ldux",
	LDX:            "ldx",
	LWA:            "lwa",

			switch inst.Op {
			case FDIV:
				inst.Op = FDIVR
			case FDIVR:
				inst.Op = FDIV
			case FSUB:
				inst.Op = FSUBR
			case FSUBR:
				inst.Op = FSUB
			case FDIVP:
				inst.Op = FDIVRP
			case FDIVRP:
				inst.Op = FDIVP
			case FSUBP:
				inst.Op = FSUBRP
			case FSUBRP:
				inst.Op = FSUBP
			}
		}

	case MOVNTSD:
		// MOVNTSD is F2 0F 2B /r.

			gwc.mu.Unlock()
			if !ok {
				continue
			}
		} else {
			qr := gwc.gatewayInterest(acc.Name, subj)
			queues = queuesa[:0]
			for i := 0; i < len(qr.qsubs); i++ {
				qsubs := qr.qsubs[i]
				queue := qsubs[0].queue
				add := true
				for _, qn := range qgroups {
					if bytes.Equal(queue, qn) {
						add = false
						break
					}
				}
				if add {

// and will not run on earlier targets.
//
(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add64F ...) => (FADD ...)
(Add32F ...) => (FADDS ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub32F ...) => (FSUBS ...)
(Sub64F ...) => (FSUB ...)

(Min(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMINJDP x y)
(Max(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMAXJDP x y)

// Combine 64 bit integer multiply and adds