// TBZ <R><t>, #<imm>, <label>
	{0x7f000000, 0x36000000, TBZ, instArgs{arg_Rt_31_1__W_0__X_1, arg_immediate_0_63_b5_b40, arg_slabel_imm14_2}, nil},
	// UDIV <Wd>, <Wn>, <Wm>
	{0xffe0fc00, 0x1ac00800, UDIV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
	// UDIV <Xd>, <Xn>, <Xm>
	{0xffe0fc00, 0x9ac00800, UDIV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
	// UMULL <Xd>, <Wn>, <Wm>
	{0xffe0fc00, 0x9ba07c00, UMULL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil},

//    bits.Div*    //
// --------------- //

func Div(hi, lo, x uint) (q, r uint) {
	// amd64:"DIVQ"
	return bits.Div(hi, lo, x)
}

func Div32(hi, lo, x uint32) (q, r uint32) {
	// arm64:"ORR","UDIV","MSUB",-"UREM"
	return bits.Div32(hi, lo, x)
}

func Div64(hi, lo, x uint64) (q, r uint64) {
	// amd64:"DIVQ"
	return bits.Div64(hi, lo, x)
}

func Div64degenerate(x uint64) (q, r uint64) {

	MOVD	$r+8(FP), R0
	MOVW	flags+0(FP), R1
	MOVW	$SYS_pipe2, R8
	SVC
	MOVW	R0, errno+16(FP)
	RET

TEXT runtime·usleep(SB),NOSPLIT,$24-4
	MOVWU	usec+0(FP), R3
	MOVD	R3, R5
	MOVW	$1000000, R4
	UDIV	R4, R3
	MOVD	R3, 8(RSP)
	MUL	R3, R4
	SUB	R4, R5
	MOVW	$1000, R4
	MUL	R4, R5
	MOVD	R5, 16(RSP)

	// nanosleep(&ts, 0)
	ADD	$8, RSP, R0
	MOVD	$0, R1
	MOVD	$SYS_nanosleep, R8
	SVC
	RET

		{name: "DIV", argLength: 2, reg: gp21, asm: "SDIV"},                                                           // arg0 / arg1, signed
		{name: "UDIV", argLength: 2, reg: gp21, asm: "UDIV"},                                                          // arg0 / arg1, unsigned

	UBFIZ $3, R22, $14, R4                     // c4367dd3
	UBFXW $3, R7, $20, R15                     // ef580353
	UBFX $33, R17, $25, R5                     // 25e661d3
	UDIVW R8, R21, R15                         // af0ac81a
	UDIV R2, R19, R21                          // 750ac29a
	UMADDL R0, R20, R17, R17                   // 3152a09b
	UMSUBL R22, R4, R3, R7                     // 6790b69b
	UMNEGL R3, R19, R1                         // 61fea39b

		{name: "HMUL", argLength: 2, reg: gp21, asm: "MULL", commutative: true},   // (arg0 * arg1) >> 32, signed
		{name: "HMULU", argLength: 2, reg: gp21, asm: "MULLU", commutative: true}, // (arg0 * arg1) >> 32, unsigned

		// udiv runtime call for soft division
		// output0 = arg0/arg1, output1 = arg0%arg1
		// see ../../../../../runtime/vlop_arm.s
		{
			name:      "CALLudiv",
			argLength: 2,
			reg: regInfo{

{"Name":"UDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"UDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},

func rewriteValueARM64_OpARM64UDIV(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (UDIV x (MOVDconst [1]))
	// result: x
	for {
		x := v_0
		if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 {
			break
		}
		v.copyOf(x)
		return true
	}
	// match: (UDIV x (MOVDconst [c]))
	// cond: isPowerOfTwo64(c)
	// result: (SRLconst [log64(c)] x)
	for {

	ir.Syms.Staticuint64s = typecheck.LookupRuntimeVar("staticuint64s")
	ir.Syms.Typedmemmove = typecheck.LookupRuntimeFunc("typedmemmove")
	ir.Syms.Udiv = typecheck.LookupRuntimeVar("udiv")                 // asm func with special ABI
	ir.Syms.WriteBarrier = typecheck.LookupRuntimeVar("writeBarrier") // struct { bool; ... }
	ir.Syms.Zerobase = typecheck.LookupRuntimeVar("zerobase")

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "UDIV",
		argLen: 2,
		asm:    arm64.AUDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30