VMOVQ		V4.H[2], R6     // 86c8ef72
	VMOVQ		V5.W[2], R7     // a7e8ef72
	VMOVQ		V6.V[1], R8     // c8f4ef72
	VMOVQ		V7.BU[0], R4    // e480f372
	VMOVQ		V7.BU[1], R4    // e484f372
	VMOVQ		V9.BU[3], R5    // 258df372
	VMOVQ		V10.HU[2], R6   // 46c9f372
	VMOVQ		V11.WU[2], R7   // 67e9f372
	VMOVQ		V31.VU[1], R8   // e8f7f372
	XVMOVQ		X1.W[2], R7     // 27c8ef76
	XVMOVQ		X6.V[2], R8     // c8e8ef76

	PSTB R1, $1, 12345678(R2)               // 061000bc9822614e
	PSTD R1, $1, 12345678(R2)               // 041000bcf422614e
	PSTFD F1, $1, 12345678(R2)              // 061000bcd822614e
	PSTFS F1, $1, 123456789(R7)             // 0610075bd027cd15
	PSTH R1, $1, 12345678(R2)               // 061000bcb022614e
	PSTQ R2, $1, 12345678(R2)               // 041000bcf042614e
	PSTW R1, $1, 12345678(R2)               // 061000bc9022614e

·xorBytes(SB), NOSPLIT, $0 MOVV dst+0(FP), R4 MOVV a+8(FP), R5 MOVV b+16(FP), R6 MOVV n+24(FP), R7 MOVV $64, R9 BGEU R7, R9, loop64 // n >= 64 tail: SRLV $1, R9 BGEU R7, R9, xor_32 // n >= 32 && n < 64 SRLV $1, R9 BGEU R7, R9, xor_16 // n >= 16 && n < 32 SRLV $1, R9 BGEU R7, R9, xor_8 // n >= 8 && n < 16 SRLV $1, R9 BGEU R7, R9, xor_4 // n >= 4 && n < 8 SRLV $1, R9 BGEU R7, R9, xor_2 // n >= 2 && n < 4 SRLV $1, R9 BGEU R7, R9, xor_1 // n = 1 loop64: MOVV (R5), R10 MOVV 8(R5), R11 MOVV 16(R5), R12 MOVV 24(R5),...

The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

<p>

		}
		// fmt.Printf("SYM %s\n", obj.Dconv(&emptyProg, 0, a))
		if p.peek() == scanner.EOF {
			return
		}
	}

	// Special register list syntax for arm: [R1,R3-R7]
	if tok.ScanToken == '[' {
		if prefix != 0 {
			p.errorf("illegal use of register list")
		}
		p.registerList(a)
		p.expectOperandEnd()
		return
	}

	// Register: R1