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Results 11 - 20 of 30 for F1 (0.01 seconds)

  1. src/cmd/asm/internal/asm/testdata/arm64.s

    	MOVD	R1, 0x44332211(R2)	// MOVD		R1, 1144201745(R2)
    	FMOVS	F1, 0x1003000(R2)	// FMOVS	F1, 16789504(R2)
    	FMOVS	F1, 0x44332211(R2)	// FMOVS	F1, 1144201745(R2)
    	FMOVD	F1, 0x1007000(R2)	// FMOVD	F1, 16805888(R2)
    	FMOVD	F1, 0x44332211(R2)	// FMOVD	F1, 1144201745(R2)
    	FMOVQ	F1, 0x1003000(R2)	// FMOVQ	F1, 16789504(R2)
    	FMOVQ	F1, 0x44332211(R2)	// FMOVQ	F1, 1144201745(R2)
    
    	MOVB	0x1000000(R1), R2	// MOVB		16777216(R1), R2
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Mon Nov 10 17:34:13 GMT 2025
    - 96.1K bytes
    - Click Count (0)
  2. src/cmd/asm/internal/asm/testdata/mips64.s

    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ABSD	F1, F2
    
    //	LFADD freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ADDD	F1, F2
    
    //	LFADD freg ',' freg ',' freg
    //	{
    //		outcode(int($1), &$2, int($4.Reg), &$6);
    //	}
    	ADDD	F1, F2, F3
    
    //	LFCMP freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	CMPEQD	F1, F2
    
    
    //
    // WORD
    //
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
    - Click Count (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64.s

    	FCVTDLU X5, F0					// 538032d2
    	FCVTSD	F0, F1					// d3001040
    	FCVTDS	F0, F1					// d3000042
    	FSGNJD	F1, F0, F2				// 53011022
    	FSGNJND	F1, F0, F2				// 53111022
    	FSGNJXD	F1, F0, F2				// 53211022
    	FMVXD	F0, X5					// d30200e2
    	FMVDX	X5, F0					// 538002f2
    	FMADDD	F1, F2, F3, F4				// 4382201a
    	FMSUBD	F1, F2, F3, F4				// 4782201a
    	FNMSUBD	F1, F2, F3, F4				// 4b82201a
    	FNMADDD	F1, F2, F3, F4				// 4f82201a
    
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Thu Nov 13 12:17:37 GMT 2025
    - 73.7K bytes
    - Click Count (0)
  4. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	PNOP                                    // 0700000000000000
    	PSTB R1, $1, 12345678(R2)               // 061000bc9822614e
    	PSTD R1, $1, 12345678(R2)               // 041000bcf422614e
    	PSTFD F1, $1, 12345678(R2)              // 061000bcd822614e
    	PSTFS F1, $1, 123456789(R7)             // 0610075bd027cd15
    	PSTH R1, $1, 12345678(R2)               // 061000bcb022614e
    	PSTQ R2, $1, 12345678(R2)               // 041000bcf042614e
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Thu Mar 23 20:52:57 GMT 2023
    - 14.3K bytes
    - Click Count (0)
  5. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	FCLASSF		F4, F5		// 85341401
    	FCLASSD		F4, F5		// 85381401
    
    	FFINTFW		F0, F1		// 01101d01
    	FFINTFV		F0, F1		// 01181d01
    	FFINTDW		F0, F1		// 01201d01
    	FFINTDV		F0, F1		// 01281d01
    	FTINTWF		F0, F1		// 01041b01
    	FTINTWD		F0, F1		// 01081b01
    	FTINTVF		F0, F1		// 01241b01
    	FTINTVD		F0, F1		// 01281b01
    
    	FMAXAF		F4, F5, F6	// a6900c01
    	FMAXAF		F4, F5		// a5900c01
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Thu Nov 27 00:46:52 GMT 2025
    - 44.5K bytes
    - Click Count (0)
  6. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    // the validate function from being run and TestRISCVValidation will report missing
    // errors.
    
    TEXT validation(SB),$0
    	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
    	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"
    
    	WORD	$-1				// ERROR "must be in range [0x0, 0xffffffff]"
    	WORD	$0x100000000			// ERROR "must be in range [0x0, 0xffffffff]"
    
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Thu Nov 13 12:17:37 GMT 2025
    - 42.1K bytes
    - Click Count (0)
  7. src/cmd/asm/internal/asm/testdata/arm.s

    //
    //	LTYPEI cond freg ',' freg
    //	{
    //		outcode($1, $2, &$3, 0, &$5);
    //	}
    	ABSF	F1, F2
    
    //	LTYPEK cond frcon ',' freg
    //	{
    //		outcode($1, $2, &$3, 0, &$5);
    //	}
    	ADDD	F1, F2
    	MOVF	$0.5, F2 // MOVF $(0.5), F2
    
    //	LTYPEK cond frcon ',' LFREG ',' freg
    //	{
    //		outcode($1, $2, &$3, $5, &$7);
    //	}
    	ADDD	F1, F2, F3
    
    //	LTYPEL cond freg ',' freg
    //	{
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Fri Dec 15 20:51:01 GMT 2023
    - 69K bytes
    - Click Count (0)
  8. docs/sts/tls.md

            Subject Public Key Info:
                Public Key Algorithm: ED25519
                    ED25519 Public-Key:
                    pub:
                        5a:91:87:b8:77:fe:d4:af:d9:c7:c7:ce:55:ae:74:
                        aa:f3:f1:fe:04:63:9b:cb:20:97:61:97:90:94:fa:
                        12:8b
            X509v3 extensions:
                X509v3 Key Usage: critical
                    Digital Signature
                X509v3 Extended Key Usage: 
    Created: Sun Dec 28 19:28:13 GMT 2025
    - Last Modified: Tue Aug 12 18:20:36 GMT 2025
    - 6K bytes
    - Click Count (1)
  9. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	MOVBU	X5, (X6)			// ERROR "unsupported unsigned store"
    	MOVHU	X5, (X6)			// ERROR "unsupported unsigned store"
    	MOVWU	X5, (X6)			// ERROR "unsupported unsigned store"
    	MOVF	F0, F1, F2			// ERROR "illegal MOV instruction"
    	MOVD	F0, F1, F2			// ERROR "illegal MOV instruction"
    	MOV	X10, X11, X12			// ERROR "illegal MOV instruction"
    	MOVW	X10, X11, X12			// ERROR "illegal MOV instruction"
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Wed Sep 24 13:21:53 GMT 2025
    - 26.8K bytes
    - Click Count (0)
  10. src/cmd/asm/internal/asm/operand_test.go

    	{"R7", "R7"},
    	{"R8", "R8"},
    	{"R9", "R9"},
    	{"R10", "R10"},
    	{"R11", "R11"},
    	{"R12", "R12"},
    	// {"R13", "R13"}, R13 is g
    	{"R14", "R14"},
    	{"R15", "R15"},
    	{"F0", "F0"},
    	{"F1", "F1"},
    	{"F2", "F2"},
    	{"F3", "F3"},
    	{"F4", "F4"},
    	{"F5", "F5"},
    	{"F6", "F6"},
    	{"F7", "F7"},
    	{"F8", "F8"},
    	{"F9", "F9"},
    	{"F10", "F10"},
    	{"F11", "F11"},
    	{"F12", "F12"},
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Tue Aug 29 18:31:05 GMT 2023
    - 23.9K bytes
    - Click Count (0)
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