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Results 21 - 30 of 197 for if64 (0.04 sec)

  1. platforms/native/platform-native/src/main/java/org/gradle/nativeplatform/platform/internal/Architectures.java

        public static final KnownArchitecture X86_64 = new KnownArchitecture("x86-64", "x86_64", "amd64", "x64");
        public static final KnownArchitecture IA_64 = new KnownArchitecture("ia-64", "ia64");
        public static final KnownArchitecture ARM_V7 = new KnownArchitecture("arm-v7", "armv7", "arm", "arm32");
        public static final KnownArchitecture AARCH64 = new KnownArchitecture("aarch64", "arm-v8", "arm64");
    
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Thu Nov 16 20:20:03 UTC 2023
    - 2.7K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/quantization/stablehlo/tests/passes/convert_func_to_bfloat16.mlir

    }
    
    // -----
    
    // CHECK-LABEL: @add_f64(%arg0: tensor<3x3xbf16>, %arg1: tensor<3x3xbf16>) -> tensor<3x3xbf16>
    func.func @add_f64(%arg0: tensor<3x3xf64>, %arg1: tensor<3x3xf64>) -> tensor<3x3xf64> {
      // CHECK-NOT: f64
      // CHECK: stablehlo.add
      %0 = stablehlo.add %arg0, %arg1: (tensor<3x3xf64>, tensor<3x3xf64>) -> tensor<3x3xf64>
      return %0 : tensor<3x3xf64>
    }
    
    // -----
    
    // CHECK-LABEL: @constant_f32() -> tensor<2x2xbf16>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Feb 08 22:40:14 UTC 2024
    - 6K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/composite_op_round_trip.mlir

        %0 = stablehlo.composite "stablehlo.add_n" %arg0 { composite_attributes = { test_int = 2 : i64, test_bool = 0 : i1, test_string = "test"}, decomposition = @add_n.impl } : (tensor<i64>) -> tensor<i64>
        return %0 : tensor<i64>
      }
      func.func private @add_n.impl(%arg0: tensor<i64>) -> tensor<i64> {
        %0 = stablehlo.constant dense<2> : tensor<i64>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Apr 24 03:40:50 UTC 2024
    - 1.1K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf-communication.mlir

    // Serialized string:
    //   "\08\01\1A\01\01\22\01\00"
    
    // CHECK-LABEL: func @host_compute
    // CHECK-SAME:  ([[ARG0:%.*]]: tensor<i32>, [[ARG1:%.*]]: tensor<i64>)
    func.func @host_compute(%arg0: tensor<i32>, %arg1: tensor<i64>) -> (tensor<f32>, tensor<f64>) {
      // CHECK:      [[INIT_TOKEN:%.*]] = mhlo.create_token
    
      // CHECK:      [[SEND_ARG0_TOKEN:%.*]] = "mhlo.send"([[ARG0]], [[INIT_TOKEN]])
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Feb 08 18:24:20 UTC 2024
    - 38.3K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf-quant.mlir

          lhs_quantization_axis = -1 : i64,
          lhs_quantization_min_val = -2147483648 : i64,
          lhs_quantization_max_val = 2147483647 : i64,
          rhs_quantization_axis = -1 : i64,
          rhs_quantization_min_val = -2147483648 : i64,
          rhs_quantization_max_val = 2147483647 : i64,
          output_quantization_axis = -1 : i64,
          output_quantization_min_val = -2147483648 : i64,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 09 01:25:29 UTC 2024
    - 37.3K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tfrt/tests/reconfig_batch_op.mlir

      // CHECK-SAME: allowed_batch_sizes = [6]
      // CHECK-SAME: batch_timeout_micros = 100000 : i64
      // CHECK-SAME: batching_queue = ""
      // CHECK-SAME: container = ""
      // CHECK-SAME: enable_large_batch_splitting = false
      // CHECK-SAME: max_batch_size = 6 : i64
      // CHECK-SAME: max_enqueued_batches = 10 : i64
      // CHECK-SAME: num_batch_threads = 2 : i64
      // CHECK-SAME: shared_name = "batch/"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 31 17:38:34 UTC 2024
    - 5.2K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/lite/tests/legalize-tf-hashtables.mlir

      // CHECK-NEXT:  return [[SIZE]] : tensor<i64>
      func.return %1 : tensor<i64>
    }
    
    // -----
    
    // Test for case with import and find ops.
    func.func @hashtable_import_then_find(%arg0: tensor<5x!tf_type.string>) -> tensor<*xi64> {
      %cst = arith.constant dense<["emerson", "lake", "palmer"]> : tensor<3x!tf_type.string>
      %cst_0 = arith.constant dense<-1> : tensor<i64>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 9.4K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/quantization/stablehlo/tests/bridge/convert_tf_quant_ops_to_mhlo.mlir

          lhs_quantization_axis = -1 : i64,
          lhs_quantization_min_val = -2147483648 : i64,
          lhs_quantization_max_val = 2147483647 : i64,
          rhs_quantization_axis = -1 : i64,
          rhs_quantization_min_val = -2147483648 : i64,
          rhs_quantization_max_val = 2147483647 : i64,
          output_quantization_axis = -1 : i64,
          output_quantization_min_val = -2147483648 : i64,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 7.2K bytes
    - Viewed (0)
  9. test/codegen/bits.go

    func bitRotateAndMask(io64 [8]uint64, io32 [4]uint32, io16 [4]uint16, io8 [4]uint8) {
    	// ppc64x: "RLDICR\t[$]0, R[0-9]*, [$]47, R"
    	io64[0] = io64[0] & 0xFFFFFFFFFFFF0000
    	// ppc64x: "RLDICL\t[$]0, R[0-9]*, [$]16, R"
    	io64[1] = io64[1] & 0x0000FFFFFFFFFFFF
    	// ppc64x: -"SRD", -"AND", "RLDICL\t[$]60, R[0-9]*, [$]16, R"
    	io64[2] = (io64[2] >> 4) & 0x0000FFFFFFFFFFFF
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 7.8K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/tensorflow/tests/tf_saved_model_freeze_assets.mlir

        "tf.InitializeTableFromTextFileV2"(%0, %arg0) {delimiter = "\09", device = "", key_index = -2 : i64, offset = 0 : i64, value_index = -1 : i64, vocab_size = 437 : i64} : (tensor<!tf_type.resource>, tensor<!tf_type.string>) -> ()
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.5K bytes
    - Viewed (0)
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