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Results 11 - 20 of 43 for vmov (0.14 sec)
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src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
RET 7. Move large constants to vector registers. Go asm uses VMOVQ/VMOVD/VMOVS to move 128-bit, 64-bit and 32-bit constants into vector registers, respectively. And for a 128-bit integer, it take two 64-bit operands, for the low and high parts separately. Examples: VMOVS $0x11223344, V0 VMOVD $0x1122334455667788, V1 VMOVQ $0x1122334455667788, $0x99aabbccddeeff00, V2 // V2=0x99aabbccddeeff001122334455667788
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/inst.go
// The Index field specifies the index number, // but the size of the fraction is not specified. // It must be inferred from the instruction and the register type. // For example, in a VMOV instruction, RegX{D5, 1} represents // the top 32 bits of the 64-bit D5 register. type RegX struct { Reg Reg Index int } func (RegX) IsArg() {} func (r RegX) String() string {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 22:23:32 UTC 2017 - 7.5K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/runtime/memclr_mips64x.s
msa_large_loop: VMOVB W0, (R1) VMOVB W0, 16(R1) VMOVB W0, 32(R1) VMOVB W0, 48(R1) VMOVB W0, 64(R1) VMOVB W0, 80(R1) VMOVB W0, 96(R1) VMOVB W0, 112(R1) ADDVU $128, R1 SGTU R6, R1, R3 BNE R3, R0, msa_large_loop BEQ R5, R0, done VMOVB W0, -128(R4) VMOVB W0, -112(R4) VMOVB W0, -96(R4) VMOVB W0, -80(R4) VMOVB W0, -64(R4) VMOVB W0, -48(R4) VMOVB W0, -32(R4) VMOVB W0, -16(R4) JMP done
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1.7K bytes - Viewed (0) -
src/cmd/compile/internal/riscv64/ggen.go
// ADD $(off), SP, T0 // ADD $(cnt), T0, T1 // loop: // MOV ZERO, (T0) // ADD $Widthptr, T0 // BNE T0, T1, loop p = pp.Append(p, riscv.AADD, obj.TYPE_CONST, 0, off, obj.TYPE_REG, riscv.REG_T0, 0) p.Reg = riscv.REG_SP p = pp.Append(p, riscv.AADD, obj.TYPE_CONST, 0, cnt, obj.TYPE_REG, riscv.REG_T1, 0) p.Reg = riscv.REG_T0 p = pp.Append(p, riscv.AMOV, obj.TYPE_REG, riscv.REG_ZERO, 0, obj.TYPE_MEM, riscv.REG_T0, 0) loop := p
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 19 15:59:22 UTC 2022 - 1.8K bytes - Viewed (0) -
src/runtime/rt0_freebsd_riscv64.s
MOV $0x800000, A0 // stacksize = 8192KB MOV $_rt0_riscv64_freebsd_lib_go(SB), A1 MOV A0, 8(X2) MOV A1, 16(X2) MOV $runtime·newosproc0(SB), T0 JALR RA, T0 restore: // Restore callee-save registers, along with X1 (LR). MOV (8*3)(X2), X1 MOV (8*4)(X2), X8 MOV (8*5)(X2), X9 MOV (8*6)(X2), X18 MOV (8*7)(X2), X19 MOV (8*8)(X2), X20 MOV (8*9)(X2), X21 MOV (8*10)(X2), X22 MOV (8*11)(X2), X23
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 28 03:17:13 UTC 2022 - 2.7K bytes - Viewed (0) -
src/runtime/memmove_riscv64.s
BNEZ X5, f_align f_loop_check: MOV $16, X9 BLT X12, X9, f_loop8_check MOV $32, X9 BLT X12, X9, f_loop16_check MOV $64, X9 BLT X12, X9, f_loop32_check f_loop64: MOV 0(X11), X14 MOV 8(X11), X15 MOV 16(X11), X16 MOV 24(X11), X17 MOV 32(X11), X18 MOV 40(X11), X19 MOV 48(X11), X20 MOV 56(X11), X21 MOV X14, 0(X10) MOV X15, 8(X10) MOV X16, 16(X10) MOV X17, 24(X10) MOV X18, 32(X10)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 09 13:57:06 UTC 2023 - 5.5K bytes - Viewed (0) -
src/internal/runtime/syscall/asm_linux_riscv64.s
// err | A2 | part of A0 TEXT ·Syscall6<ABIInternal>(SB),NOSPLIT,$0-80 MOV A0, A7 MOV A1, A0 MOV A2, A1 MOV A3, A2 MOV A4, A3 MOV A5, A4 MOV A6, A5 ECALL MOV $-4096, T0 BLTU T0, A0, err // r1 already in A0 // r2 already in A1 MOV ZERO, A2 // errno RET err: SUB A0, ZERO, A2 // errno MOV $-1, A0 // r1 MOV ZERO, A1 // r2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 21 21:28:32 UTC 2024 - 969 bytes - Viewed (0)