//
// PLD
//
//	LTYPEPLD oreg
//	{
//		outcode($1, Always, &$2, 0, &nullgen);
//	}
	PLD	(R1)
	PLD	4(R1)

//
// RET
//
//	LTYPEA cond
//	{
//		outcode($1, $2, &nullgen, 0, &nullgen);
//	}
	BEQ	2(PC)
	RET

// More B/BL cases, and canonical names JMP, CALL.

	BEQ	2(PC)
	B	foo(SB) // JMP foo(SB)
	BL	foo(SB) // CALL foo(SB)
	BEQ	2(PC)
	JMP	foo(SB)

                if (canon.equalsIgnoreCase(f.canon)) {
                    try {
                        ret = getAddress().equals(f.getAddress());
                    } catch (final UnknownHostException uhe) {
                        ret = getServer().equalsIgnoreCase(f.getServer());
                    }
                    return ret;
                }
            }
        }

        return false;
    }
    /*

	AUTIB1716	R0                                       // ERROR "illegal combination"
	SB	$1                                               // ERROR "illegal combination"

	VRGATHEREI16VV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VRGATHERVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
	VRGATHERVI	$16, V2, V4, V3			// ERROR "invalid vector mask register"

	if name == "." {
		return dotFile
	}

	dir, elem, _ := split(name)
	files := r.fileList
	i, _ := slices.BinarySearchFunc(files, dir, func(a fileListEntry, dir string) (ret int) {
		idir, ielem, _ := split(a.name)
		if dir != idir {
			return strings.Compare(idir, dir)
		}
		return strings.Compare(ielem, elem)
	})
	if i < len(files) {
		fname := files[i].name

	VP4DPWSSDS (SP), [Z14-Z17], K1, Z0                 // 62f20f49530424
	VP4DPWSSDS -7(DI)(R8*1), [Z24-Z27], K1, Z0         // 62b23f41538407f9ffffff
	VP4DPWSSDS (SP), [Z24-Z27], K1, Z0                 // 62f23f41530424

	VSCATTERPF1QPS K3, (BP)(Z10*2)                     // 62b27d4bc7745500
	VSCATTERPF1QPS K3, (R10)(Z29*8)                    // 62927d43c734ea
	VSCATTERPF1QPS K3, (R14)(Z29*8)                    // 62927d43c734ee

	VCLZLSBB V1,R2                  // 10400e02
	VCTZLSBB V1,R2                  // 10410e02

	XSMAXJDP VS1,VS2,VS3            // f0611480
	XSMINJDP VS1,VS2,VS3            // f06114c0

	VMV2RV		X10, V10			// ERROR "expected vector register in vs2 position"
	VMV4RV		X10, V4				// ERROR "expected vector register in vs2 position"
	VMV8RV		X10, V0				// ERROR "expected vector register in vs2 position"

	VPOPCNTQ Z3, K2, Z9                                // 6272fd4a55cb
	VPOPCNTQ 17(SP), K2, Z9                            // 6272fd4a558c2411000000
	VPOPCNTQ -17(BP)(SI*4), K2, Z9                     // 6272fd4a558cb5efffffff