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Results 61 - 70 of 159 for reg1 (0.05 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD"}, // move float64 to int64 (no conversion)
    		{name: "FMOVSgpfp", argLength: 1, reg: gpfp, asm: "FMOVS"}, // move 32bits from int to float reg (no conversion)
    		{name: "FMOVSfpgp", argLength: 1, reg: fpgp, asm: "FMOVS"}, // move 32bits from float to int reg, zero extend (no conversion)
    
    		// conversions
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo_patterns.td

                  (MHLO_CompareOp:$rnz $rem1, (MHLO_ConstantOp $cst2), MHLO_ComparisonDirectionValue<"NE">, $compare_type3)),
                (MHLO_AddOp $rem2, $arg1),
                $rem3),
              (TF_FloorModOp $arg, $arg1),
              [(ValueEquals<"0.0"> $cst),
               (ValueEquals<"0.0"> $cst1),
               (ValueEquals<"0.0"> $cst2),
               (SameValue $rem, $rem1),
               (SameValue $rem, $rem2),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Feb 03 08:58:22 UTC 2024
    - 34K bytes
    - Viewed (0)
  3. tensorflow/c/kernels/bitcast_op_test.cc

      ASSERT_EQ("[3,4]", c.DebugString(input_shapes[0]));
      TF_CHECK_OK(reg->shape_inference_fn(&c));
      ASSERT_EQ("[3,4,8]", c.DebugString(c.output(0)));
    }
    
    TEST(BitcastOpTest, TestShapeInference_SmallerShape) {
      const OpRegistrationData* reg;
      TF_CHECK_OK(OpRegistry::Global()->LookUp("Bitcast", &reg));
      OpDef op_def = reg->op_def;
      NodeDef def;
      TF_CHECK_OK(NodeDefBuilder("dummy", &op_def)
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Jul 18 15:10:51 UTC 2022
    - 5.5K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm/list5.go

    	obj.RegisterRegisterList(obj.RegListARMLo, obj.RegListARMHi, rlconv)
    	obj.RegisterOpSuffix("arm", obj.CConvARM)
    }
    
    func rconv(r int) string {
    	if r == 0 {
    		return "NONE"
    	}
    	if r == REGG {
    		// Special case.
    		return "g"
    	}
    	if REG_R0 <= r && r <= REG_R15 {
    		return fmt.Sprintf("R%d", r-REG_R0)
    	}
    	if REG_F0 <= r && r <= REG_F15 {
    		return fmt.Sprintf("F%d", r-REG_F0)
    	}
    
    	switch r {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jun 04 07:25:06 UTC 2020
    - 3.1K bytes
    - Viewed (0)
  5. src/test/java/org/codelibs/fess/dict/kuromoji/KuromojiFileTest.java

        @Override
        protected void setUp() throws Exception {
            file1 = File.createTempFile("kuromoji_", ".txt");
            FileUtil.write(
                    file1.getAbsolutePath(),
                    "token1,seg1,reading1,pos1\ntoken2,seg2,reading2,pos2\ntoken3,seg3,reading3,pos3"
                            .getBytes(Constants.UTF_8));
        }
    
        @Override
        protected void tearDown() throws Exception {
            file1.delete();
    Registered: Wed Jun 12 13:08:18 UTC 2024
    - Last Modified: Thu Feb 22 01:37:57 UTC 2024
    - 7.3K bytes
    - Viewed (0)
  6. docs/iam/opa.md

    ```
    
    ### 2. Create a sample OPA Policy
    
    In another terminal, create a policy that allows root user all access and for all other users denies `PutObject`:
    
    ```sh
    cat > example.rego <<EOF
    package httpapi.authz
    
    import input
    
    default allow = false
    
    # Allow the root user to perform any action.
    allow {
     input.owner == true
    }
    
    Registered: Sun Jun 16 00:44:34 UTC 2024
    - Last Modified: Sun Jul 17 15:43:14 UTC 2022
    - 2.3K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/loong64/list.go

    	"fmt"
    )
    
    func init() {
    	obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST+1, rconv)
    	obj.RegisterOpcode(obj.ABaseLoong64, Anames)
    }
    
    func rconv(r int) string {
    	if r == 0 {
    		return "NONE"
    	}
    	if r == REGG {
    		// Special case.
    		return "g"
    	}
    	if REG_R0 <= r && r <= REG_R31 {
    		return fmt.Sprintf("R%d", r-REG_R0)
    	}
    	if REG_F0 <= r && r <= REG_F31 {
    		return fmt.Sprintf("F%d", r-REG_F0)
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 11 20:11:34 UTC 2022
    - 931 bytes
    - Viewed (0)
  8. src/cmd/internal/obj/x86/obj6.go

    		p.To.Type = obj.TYPE_REG
    		p.To.Reg = reg
    		p.To.Offset = 0
    		p.To.Sym = nil
    		p1 := obj.Appendp(p, newprog)
    		p1.As = lea
    		p1.From.Type = obj.TYPE_MEM
    		p1.From.Offset = offset
    		p1.From.Reg = reg
    		p1.To.Type = obj.TYPE_REG
    		p1.To.Reg = reg
    		p2 := obj.Appendp(p1, newprog)
    		p2.As = obj.ACALL
    		p2.To.Type = obj.TYPE_REG
    		p2.To.Reg = reg
    	}
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Sep 08 18:36:45 UTC 2023
    - 40.9K bytes
    - Viewed (0)
  9. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go

    		return nil
    	case TypeReg:
    		return R0 + Reg(a.BitFields.Parse(i))
    	case TypeCondRegBit:
    		return Cond0LT + CondReg(a.BitFields.Parse(i))
    	case TypeCondRegField:
    		return CR0 + CondReg(a.BitFields.Parse(i))
    	case TypeFPReg:
    		return F0 + Reg(a.BitFields.Parse(i))
    	case TypeVecReg:
    		return V0 + Reg(a.BitFields.Parse(i))
    	case TypeVecSReg:
    		return VS0 + Reg(a.BitFields.Parse(i))
    	case TypeVecSpReg:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 5.6K bytes
    - Viewed (0)
  10. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go

    	return opstr[o]
    }
    
    // An Arg is a single instruction argument, one of these types: Reg, CondReg, SpReg, Imm, PCRel, Label, or Offset.
    type Arg interface {
    	IsArg()
    	String() string
    }
    
    // An Args holds the instruction arguments.
    // If an instruction has fewer than 6 arguments,
    // the final elements in the array are nil.
    type Args [6]Arg
    
    // A Reg is a single register. The zero value means R0, not the absence of a register.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 03 01:35:44 UTC 2021
    - 4.5K bytes
    - Viewed (0)
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