TEXT main(SB),NOSPLIT|NOFRAME,$0
	// in external linking, glibc jumps to main with argc in R4
	// and argv in R5

	// initialize REGSB = PC&0xffffffff00000000
	BGEZAL	R0, 1(PC)
	SRLV	$32, R31, RSB
	SLLV	$32, RSB

	MOVV	$runtime·rt0_go(SB), R1

	// riscv64:"FNMADDD",-"FNMSUBD"
	return math.FMA(x, -y, -z)
}

func fromFloat64(f64 float64) uint64 {
	// amd64:"MOVQ\tX.*, [^X].*"
	// arm64:"FMOVD\tF.*, R.*"
	// ppc64x:"MFVSRD"
	// mips64/hardfloat:"MOVV\tF.*, R.*"
	return math.Float64bits(f64+1) + 1
}

func fromFloat32(f32 float32) uint32 {
	// amd64:"MOVL\tX.*, [^X].*"
	// arm64:"FMOVS\tF.*, R.*"
	// mips64/hardfloat:"MOVW\tF.*, R.*"

}

func genMIPS(_64bit bool) {
	mov := "MOVW"
	movf := "MOVF"
	add := "ADD"
	sub := "SUB"
	r28 := "R28"
	regsize := 4
	softfloat := "GOMIPS_softfloat"
	if _64bit {
		mov = "MOVV"
		movf = "MOVD"
		add = "ADDV"
		sub = "SUBV"
		r28 = "RSB"
		regsize = 8
		softfloat = "GOMIPS64_softfloat"
	}

	// Add integer registers R1-R22, R24-R25, R28

	&& !config.noDuffDevice && logLargeCopy(v, s)  =>
	(DUFFCOPY [16 * (128 - s/8)] dst src mem)
// 16 and 128 are magic constants.  16 is the number of bytes to encode:
//	MOVV	(R1), R23
//	ADDV	$8, R1
//	MOVV	R23, (R2)
//	ADDV	$8, R2
// and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.

// large or unaligned move uses a loop
(Move [s] {t} dst src mem)

		o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))

	case 40: // word
		o1 = uint32(c.regoff(&p.From))

	case 47: // movv r,fr
		a := OP_TEN(8, 1322) // movgr2fr.d
		o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))

	case 48: // movv fr,r
		a := OP_TEN(8, 1326) // movfr2gr.d
		o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))

	case 49:
		if p.As == ANOOP {

	&& !config.noDuffDevice && logLargeCopy(v, s)  =>
	(DUFFCOPY [16 * (128 - s/8)] dst src mem)
// 16 and 128 are magic constants.  16 is the number of bytes to encode:
//	MOVV	(R1), R23
//	ADDV	$8, R1
//	MOVV	R23, (R2)
//	ADDV	$8, R2
// and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.

// large or unaligned move uses a loop
(Move [s] {t} dst src mem)

		case "loong64", "mips", "mipsle", "mips64", "mips64le":
			switch op {
			case "MOVB", "MOVBU":
				src = 1
			case "MOVH", "MOVHU":
				src = 2
			case "MOVW", "MOVWU", "MOVF":
				src = 4
			case "MOVV", "MOVD":
				src = 8
			}
		case "s390x":
			switch op {
			case "MOVB", "MOVBZ":
				src = 1
			case "MOVH", "MOVHZ":
				src = 2
			case "MOVW", "MOVWZ", "FMOVS":
				src = 4

	MOVD	$3, R1
	RET

GLOBL	·alignPcFnAddr(SB),RODATA,$8
DATA	·alignPcFnAddr(SB)/8,$·alignPc(SB)
`,
	"loong64": `
#include "textflag.h"

TEXT	·alignPc(SB),NOSPLIT, $0-0
	MOVV	$2, R4
	PCALIGN	$512
	MOVV	$3, R5
	RET

GLOBL	·alignPcFnAddr(SB),RODATA,$8
DATA	·alignPcFnAddr(SB)/8,$·alignPc(SB)
`,
}

// TestFuncAlign verifies that the address of a function can be aligned

	case 42: /* movw fcr,r */
		o1 = OP_RRR(SP(2, 1)|(2<<21), p.To.Reg, obj.REG_NONE, p.From.Reg) /* mfcc1 */

	case 47: /* movv r,fr */
		a := SP(2, 1) | (5 << 21) /* dmtc1 */
		o1 = OP_RRR(a, p.From.Reg, obj.REG_NONE, p.To.Reg)

	case 48: /* movv fr,r */
		a := SP(2, 1) | (1 << 21) /* dmtc1 */
		o1 = OP_RRR(a, p.To.Reg, obj.REG_NONE, p.From.Reg)

	case 49: /* undef */