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src/math/fma.go
sign = uint32(b >> 63) exp = int32(b>>52) & mask mantissa = b & fracMask if exp == 0 { // Normalize value if subnormal. shift := uint(bits.LeadingZeros64(mantissa) - 11) mantissa <<= shift exp = 1 - int32(shift) } else { // Add implicit 1 bit mantissa |= 1 << 52 } return } // FMA returns x * y + z, computed with only one rounding.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 05 22:05:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 37.8K bytes - Viewed (0) -
platforms/native/platform-native/src/testFixtures/groovy/org/gradle/nativeplatform/fixtures/app/Swift3WithXCTest.groovy
*/ package org.gradle.nativeplatform.fixtures.app class Swift3WithXCTest extends MainWithXCTestSourceElement { final Swift3 main final XCTestSourceElement test Swift3WithXCTest(String projectName) { super(projectName) this.main = new Swift3(projectName) this.test = new XCTestSourceElement(projectName) { @Override
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Thu Nov 16 20:20:03 UTC 2023 - 1.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "ANDshiftRAreg", argLength: 3, reg: gp31, asm: "AND"}, // arg0 & (arg1>>arg2), signed shift {name: "ORshiftLLreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1<<arg2 {name: "ORshiftRLreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1>>arg2, unsigned shift {name: "ORshiftRAreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1>>arg2, signed shift
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/compress/flate/testdata/huffman-text-shift.golden
Klaus Post <******@****.***> 1457448890 +0100
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 11 17:40:52 UTC 2016 - 231 bytes - Viewed (0) -
src/compress/flate/testdata/huffman-text-shift.in
Klaus Post <******@****.***> 1457448890 +0100
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 11 17:40:52 UTC 2016 - 253 bytes - Viewed (0) -
src/compress/flate/testdata/huffman-shifts.dyn.expect-noinput
Klaus Post <******@****.***> 1457448890 +0100
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 11 17:40:52 UTC 2016 - 32 bytes - Viewed (0) -
src/compress/flate/testdata/huffman-shifts.wb.expect-noinput
Klaus Post <******@****.***> 1457448890 +0100
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 11 17:40:52 UTC 2016 - 32 bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/Wasm.rules
(Rsh8Ux64 [c] x y) => (Rsh64Ux64 [c] (ZeroExt8to64 x) y) (Rsh8Ux(32|16|8) [c] x y) => (Rsh64Ux64 [c] (ZeroExt8to64 x) (ZeroExt(32|16|8)to64 y)) // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. // We implement this by setting the shift value to (width - 1) if the shift value is >= width. (Rsh64x64 x y) && shiftIsBounded(v) => (I64ShrS x y) (Rsh64x64 x (I64Const [c])) && uint64(c) < 64 => (I64ShrS x (I64Const [c]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 17 03:56:57 UTC 2023 - 16.9K bytes - Viewed (0) -
tests/test_tutorial/test_schema_extra_example/test_tutorial004_an.py
Registered: Mon Jun 17 08:32:26 UTC 2024 - Last Modified: Fri Jul 07 17:12:13 UTC 2023 - 6.9K bytes - Viewed (0)