(OR x (SLLconst [c] y)) => (ORshiftLL x y [c])
(OR x (SRLconst [c] y)) => (ORshiftRL x y [c])
(OR x (SRAconst [c] y)) => (ORshiftRA x y [c])
(OR x (SLL y z)) => (ORshiftLLreg x y z)
(OR x (SRL y z)) => (ORshiftRLreg x y z)
(OR x (SRA y z)) => (ORshiftRAreg x y z)
(XOR x (SLLconst [c] y)) => (XORshiftLL x y [c])
(XOR x (SRLconst [c] y)) => (XORshiftRL x y [c])
(XOR x (SRAconst [c] y)) => (XORshiftRA x y [c])

		{name: "ANDshiftRAreg", argLength: 3, reg: gp31, asm: "AND"}, // arg0 & (arg1>>arg2), signed shift
		{name: "ORshiftLLreg", argLength: 3, reg: gp31, asm: "ORR"},  // arg0 | arg1<<arg2
		{name: "ORshiftRLreg", argLength: 3, reg: gp31, asm: "ORR"},  // arg0 | arg1>>arg2, unsigned shift
		{name: "ORshiftRAreg", argLength: 3, reg: gp31, asm: "ORR"},  // arg0 | arg1>>arg2, signed shift

			}
			z := v_1.Args[1]
			y := v_1.Args[0]
			v.reset(OpARMORshiftLLreg)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	// match: (OR x (SRL y z))
	// result: (ORshiftRLreg x y z)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != OpARMSRL {
				continue
			}
			z := v_1.Args[1]
			y := v_1.Args[0]

				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "ORshiftRLreg",
		argLen: 3,
		asm:    arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14