{name: "SUB", argLength: 2, reg: gp21, asm: "SUB", clobberFlags: true},                                                                                       // arg0 - arg1
		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", clobberFlags: true},                                                                                     // arg0 - arg1

		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1
		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"},                  // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits

		// M extension. H means high (i.e., it returns the top bits of

	"STI",
	"STMXCSR",
	"STOSB",
	"STOSL",
	"STOSQ",
	"STOSW",
	"STRL",
	"STRQ",
	"STRW",
	"SUBB",
	"SUBL",
	"SUBPD",
	"SUBPS",
	"SUBQ",
	"SUBSD",
	"SUBSS",
	"SUBW",
	"SWAPGS",
	"SYSCALL",
	"SYSENTER",
	"SYSENTER64",
	"SYSEXIT",
	"SYSEXIT64",
	"SYSRET",
	"TESTB",
	"TESTL",
	"TESTQ",
	"TESTW",
	"TPAUSE",
	"TZCNTL",
	"TZCNTQ",

	SUBW $7, (R11)                          // 6641832b07
	SUBW $7, DX                             // 6683ea07
	SUBW $7, R11                            // 664183eb07
	SUBW DX, (BX)                           // 662913
	SUBW R11, (BX)                          // 6644291b
	SUBW DX, (R11)                          // 66412913
	SUBW R11, (R11)                         // 6645291b

	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	ADDSW	R19.UXTW, R14, R17              // d141332b
	ADDS	R12.SXTX, R3, R1                // 61e02cab
	SUB	R19.UXTH<<4, R2, R21            // 553033cb
	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
	SUBS	R3.UXTX, R8, R9                 // 096123eb
	SUBSW	R17.UXTH, R15, R21              // f521316b
	SUBW	ZR<<14, R19, R13                // 6d3a1f4b
	CMP	R2.SXTH, R13                    // bfa122eb
	CMN	R1.SXTX<<2, R10                 // 5fe921ab

	v_0 := v.Args[0]
	b := v.Block
	// match: (SUBW x (MOVDconst [c]))
	// result: (SUBWconst x [int32(c)])
	for {
		x := v_0
		if v_1.Op != OpS390XMOVDconst {
			break
		}
		c := auxIntToInt64(v_1.AuxInt)
		v.reset(OpS390XSUBWconst)
		v.AuxInt = int32ToAuxInt(int32(c))
		v.AddArg(x)
		return true
	}
	// match: (SUBW (MOVDconst [c]) x)

	VEOR	V0.B16, V2.B16, V0.B16
	VEOR	V4.B16, V6.B16, V4.B16
	VEOR	V4.B16, V0.B16, V0.B16

	VMOV	V0.D[0], R0
	RET

TEXT runtime·procyield(SB),NOSPLIT,$0-0
	MOVWU	cycles+0(FP), R0
again:
	YIELD
	SUBW	$1, R0
	CBNZ	R0, again
	RET

// Save state of caller into g->sched,
// but using fake PC from systemstack_switch.
// Must only be called from functions with no locals ($0)

	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SUBW x (MOVDconst [0]))
	// result: (ADDIW [0] x)
	for {
		x := v_0
		if v_1.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 {
			break
		}
		v.reset(OpRISCV64ADDIW)
		v.AuxInt = int64ToAuxInt(0)
		v.AddArg(x)
		return true
	}
	// match: (SUBW (MOVDconst [0]) x)
	// result: (NEGW x)
	for {

			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "SUBW",
		argLen: 2,
		asm:    riscv.ASUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30