"VLD4R",
	"VMOV",
	"VMOVD",
	"VMOVI",
	"VMOVQ",
	"VMOVS",
	"VORR",
	"VPMULL",
	"VPMULL2",
	"VRAX1",
	"VRBIT",
	"VREV16",
	"VREV32",
	"VREV64",
	"VSHL",
	"VSLI",
	"VSRI",
	"VST1",
	"VST2",
	"VST3",
	"VST4",
	"VSUB",
	"VTBL",
	"VTBX",
	"VTRN1",
	"VTRN2",
	"VUADDLV",
	"VUADDW",
	"VUADDW2",
	"VUMAX",
	"VUMIN",
	"VUSHLL",
	"VUSHLL2",

	VSLDBI V1, V2, $3, V3                   // 106110d6
	VSLQ V1, V2, V3                         // 10611105
	VSRAQ V1, V2, V3                        // 10611305
	VSRDBI V1, V2, $3, V4                   // 108112d6
	VSRQ V1, V2, V3                         // 10611205
	VSTRIBL V1, V2                          // 1040080d
	VSTRIBLCC V1, V2                        // 10400c0d
	VSTRIBR V1, V2                          // 1041080d

	VAQ	V1, V2                  // e721200040f3
	VSB	V3, V4, V4              // e744300000f7
	VSH	V3, V4, V4              // e744300010f7
	VSF	V3, V4, V4              // e744300020f7
	VSG	V3, V4, V4              // e744300030f7
	VSQ	V3, V4, V4              // e744300040f7
	VSB	V1, V2                  // e722100000f7
	VSH	V1, V2                  // e722100010f7
	VSF	V1, V2                  // e722100020f7

	LXVD2X	(R0)(R9),V2
	VCMPEQUBCC	V2,V1,V6
	BNE	CR6,foundat0		// Match found at R8+48 bytes, jump out

	BR	notfound


cmp8:	// Length 8 - 15
#ifdef GOPPC64_power10
	// Load all the bytes into a single VSR in BE order.
	SLD	$56,R4,R5
	LXVLL	R3,R5,V2
	// Compare and count the number which don't match.
	VCMPEQUB	V2,V1,V6
	VCLZLSBB	V6,R3
	// If count is the number of bytes, or more. No matches are found.
	CMPU	R3,R4

	ADD     $-2, R4, R16
	PCALIGN $16
loopback:
	ADD     $-1, R8, R10
	SLD     $3, R10
	LXVD2X  (R6)(R10), VS32 // load x[i-1], x[i]
	SLD     $3, R8, R12
	LXVD2X  (R6)(R12), VS33 // load x[i], x[i+1]

	VSRD    V0, V4, V3      // x[i-1]>>s, x[i]>>s
	VSLD    V1, V2, V5      // x[i]<<ŝ, x[i+1]<<ŝ
	VOR     V3, V5, V5      // Or(|) the two registers together
	STXVD2X VS37, (R3)(R10) // store into z[i-1] and z[i]

	VSEL   X1, T1, SEL1, T1   \
	VSEL   ZER, T2, SEL1, T2  \
	                          \
	VSLDB  $15, T2, ZER, TT1  \
	VSLDB  $15, T1, ZER, TT0  \
	VREPIB $1, SEL1           \
	VSRL   SEL1, T0, T0       \
	VSRL   SEL1, T1, T1       \
	VREPIB $7, SEL1           \
	VSL    SEL1, TT0, TT0     \
	VSL    SEL1, TT1, TT1     \
	VO     T0, TT0, T0        \
	VO     T1, TT1, T1

	"XSCVQPUQZ",
	"XSCVQPSQZ",
	"XSCMPGTQP",
	"XSCMPGEQP",
	"XSCMPEQQP",
	"VSTRIHRCC",
	"VSTRIHR",
	"VSTRIHLCC",
	"VSTRIHL",
	"VSTRIBRCC",
	"VSTRIBR",
	"VSTRIBLCC",
	"VSTRIBL",
	"VSRQ",
	"VSRDBI",
	"VSRAQ",
	"VSLQ",
	"VSLDBI",
	"VRLQNM",
	"VRLQMI",
	"VRLQ",
	"VPEXTD",
	"VPDEPD",
	"VMULOUD",
	"VMULOSD",
	"VMULLD",
	"VMULHUW",
	"VMULHUD",
	"VMULHSW",

	VSEL     T1, X1, SEL1, T1   \
	VSEL     T2, ZER, SEL1, T2  \
	                            \
	VSLDOI   $15, T2, ZER, TT1  \
	VSLDOI   $15, T1, ZER, TT0  \
	VSPLTISB $1, SEL1           \
	VSR      T0, SEL1, T0       \ // VSRL
	VSR      T1, SEL1, T1       \
	VSPLTISB $7, SEL1           \ // VREPIB
	VSL      TT0, SEL1, TT0     \
	VSL      TT1, SEL1, TT1     \
	VOR      T0, TT0, T0        \
	VOR      T1, TT1, T1

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