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Results 11 - 20 of 36 for imm5 (0.04 sec)
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src/cmd/vendor/golang.org/x/arch/x86/x86asm/intel.go
} } } } switch inst.Op { case AAM, AAD: if imm, ok := iargs[0].(Imm); ok { if inst.DataSize == 32 { iargs[0] = Imm(uint32(int8(imm))) } else if inst.DataSize == 16 { iargs[0] = Imm(uint16(int8(imm))) } } case PUSH: if imm, ok := iargs[0].(Imm); ok { iargs[0] = Imm(uint32(imm)) } } for _, p := range inst.Prefix { if p&PrefixImplicit != 0 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 22:23:32 UTC 2017 - 11.7K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go
op = "int3" } case CMPPS, CMPPD, CMPSD_XMM, CMPSS: imm, ok := inst.Args[2].(Imm) if ok && 0 <= imm && imm < 8 { inst.Args[2] = nil op = cmppsOps[imm] + op[3:] } case PCLMULQDQ: imm, ok := inst.Args[2].(Imm) if ok && imm&^0x11 == 0 { inst.Args[2] = nil op = pclmulqOps[(imm&0x10)>>3|(imm&1)] } case XLATB: if markLastImplicit(&inst, PrefixAddrSize) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 21.4K bytes - Viewed (0) -
src/cmd/covdata/subtractintersect.go
pkeys = append(pkeys, k) } // Remove anything from pmm not found in imm. We don't need to // go the other way (removing things from imm not found in pmm) // since we don't add anything to imm if there is no pmm entry. for _, k := range pkeys { if _, found := s.imm[k]; !found { delete(s.mm.pod.pmm, k) } } s.imm = nil }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 12 12:50:46 UTC 2022 - 5.5K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9_gtables.go
o1 |= uint32(p.To.Reg&0x1f) << 21 // T o1 |= uint32(p.From.Offset&0x1) << 17 // IX o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0xffff) << 0 // imm0 o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0 // imm1 out[1] = o1 out[0] = o0 } // xxspltiw XT,IMM32 func type_xxspltiw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 16 20:18:50 UTC 2022 - 42.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/inst.go
} // An Imm is an integer constant. type Imm uint32 func (Imm) IsArg() {} func (i Imm) String() string { return fmt.Sprintf("#%#x", uint32(i)) } // An ImmAlt is an alternate encoding of an integer constant. type ImmAlt struct { Val uint8 Rot uint8 } func (ImmAlt) IsArg() {} func (i ImmAlt) Imm() Imm { v := uint32(i.Val) r := uint(i.Rot)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 22:23:32 UTC 2017 - 7.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
buf.WriteString(opName) l := inst.Args[3].(Imm) if l == 0 { // L == 0 is an extended mnemonic for the same. asm := fmt.Sprintf(" %s,%s,%s", gnuArg(&inst, 0, inst.Args[0], PC), gnuArg(&inst, 1, inst.Args[1], PC), gnuArg(&inst, 2, inst.Args[2], PC)) buf.WriteString(asm) startArg = 4 } case "sync": lsc := inst.Args[0].(Imm)<<4 | inst.Args[1].(Imm) switch lsc { case 0x00:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 12.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 17K bytes - Viewed (0) -
src/crypto/internal/bigmod/_asm/nat_amd64_asm.go
Comment("Iteration " + strconv.Itoa(i)) hi, lo := RDX, RAX // implicit MULQ inputs and outputs MOVQ(x.Offset(i*8), lo) MULQ(y) ADDQ(z.Offset(i*8), lo) ADCQ(Imm(0), hi) ADDQ(carry, lo) ADCQ(Imm(0), hi) MOVQ(hi, carry) MOVQ(lo, z.Offset(i*8)) } Store(carry, ReturnIndex(0)) RET() Label("adx") // The ADX strategy implements the following function, where c1 and c2 are
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 22:37:58 UTC 2023 - 2.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL $4, R1, R2 // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $4, R1 // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
ROTRV R16, R9 // 02094856 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL $19, R22, R21 // 0016acc0 SLLV $19, R22, R21 // 0016acf8 SRL $31, R6, R17 // 00068fc2 SRLV $31, R6, R17 // 00068ffa SRA $8, R8, R19 // 00089a03 SRAV $19, R8, R7 // 00083cfb ROTR $12, R8, R3 // 00281b02 ROTRV $8, R22, R22 // 0036b23a // LSHW imm ',' rreg // {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0)