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Results 11 - 20 of 213 for dX (0.04 sec)

  1. src/runtime/sys_plan9_amd64.s

    	//	func f(x uint64) (uint64, uint64) { return x/1000000000, x%1000000000 }
    	// adapted to reduce duplication
    	MOVQ	AX, CX
    	MOVQ	$1360296554856532783, AX
    	MULQ	CX
    	ADDQ	CX, DX
    	RCRQ	$1, DX
    	SHRQ	$29, DX
    	MOVQ	DX, sec+0(FP)
    	IMULQ	$1000000000, DX
    	SUBQ	DX, CX
    	MOVL	CX, nsec+8(FP)
    	RET
    
    TEXT runtime·notify(SB),NOSPLIT,$0
    	MOVQ	$28, BP
    	SYSCALL
    	MOVL	AX, ret+8(FP)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 01 16:41:22 UTC 2023
    - 4.6K bytes
    - Viewed (0)
  2. src/math/big/arith_amd64.s

    	MULQ R9
    	ADDQ CX, AX
    	ADCQ $0, DX
    	MOVQ AX, (0*8)(R10)(BX*8)
    	MOVQ DX, CX
    	MOVQ (1*8)(R8)(BX*8), AX
    	MULQ R9
    	ADDQ CX, AX
    	ADCQ $0, DX
    	MOVQ AX, (1*8)(R10)(BX*8)
    	MOVQ DX, CX
    	MOVQ (2*8)(R8)(BX*8), AX
    	MULQ R9
    	ADDQ CX, AX
    	ADCQ $0, DX
    	MOVQ AX, (2*8)(R10)(BX*8)
    	MOVQ DX, CX
    	MOVQ (3*8)(R8)(BX*8), AX
    	MULQ R9
    	ADDQ CX, AX
    	ADCQ $0, DX
    	MOVQ AX, (3*8)(R10)(BX*8)
    	MOVQ DX, CX
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:27 UTC 2023
    - 9.1K bytes
    - Viewed (0)
  3. src/internal/bytealg/indexbyte_amd64.s

    	PMOVMSKB X1, DX	// Move result bits to integer register.
    	MOVL	BX, CX
    	SHLL	CX, DX
    	SHRL	$16, DX	// Shift desired bits down to bottom of register.
    	BSFL	DX, DX	// Find first set bit.
    	JZ	failure	// No set bit, failure.
    	MOVQ	DX, (R8)
    	RET
    
    avx2:
    #ifndef hasAVX2
    	CMPB   internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1
    	JNE sse
    #endif
    	MOVD AX, X0
    	LEAQ -32(SI)(BX*1), R11
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 01 19:06:01 UTC 2023
    - 3.1K bytes
    - Viewed (0)
  4. src/crypto/internal/edwards25519/field/fe_amd64.s

    	ADCQ   DX, SI
    
    	// r0 += 19×a4×b1
    	MOVQ   32(CX), AX
    	IMUL3Q $0x13, AX, AX
    	MULQ   8(BX)
    	ADDQ   AX, DI
    	ADCQ   DX, SI
    
    	// r1 = a0×b1
    	MOVQ (CX), AX
    	MULQ 8(BX)
    	MOVQ AX, R9
    	MOVQ DX, R8
    
    	// r1 += a1×b0
    	MOVQ 8(CX), AX
    	MULQ (BX)
    	ADDQ AX, R9
    	ADCQ DX, R8
    
    	// r1 += 19×a2×b4
    	MOVQ   16(CX), AX
    	IMUL3Q $0x13, AX, AX
    	MULQ   32(BX)
    	ADDQ   AX, R9
    	ADCQ   DX, R8
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  5. src/internal/bytealg/count_amd64.s

    	MOVOU	(SI), X1
    	// Compare target byte with each byte in data.
    	PCMPEQB	X0, X1
    	// Move result bits to integer register.
    	PMOVMSKB X1, DX
    	// Apply mask
    	ANDQ R10, DX
    	POPCNTL DX, DX
    	// Directly return DX, we don't need to accumulate
    	// since we have <16 bytes.
    	MOVQ	DX, (R8)
    	RET
    endzero:
    	MOVQ $0, (R8)
    	RET
    
    endofpage:
    	// We must ignore low bytes as they aren't part of our slice.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Oct 06 20:54:43 UTC 2023
    - 4.7K bytes
    - Viewed (0)
  6. src/crypto/sha1/sha1block_amd64.s

    	ROUND2(AX, BX, CX, DX, BP, 30)
    	ROUND2(BP, AX, BX, CX, DX, 31)
    	ROUND2(DX, BP, AX, BX, CX, 32)
    	ROUND2(CX, DX, BP, AX, BX, 33)
    	ROUND2(BX, CX, DX, BP, AX, 34)
    	ROUND2(AX, BX, CX, DX, BP, 35)
    	ROUND2(BP, AX, BX, CX, DX, 36)
    	ROUND2(DX, BP, AX, BX, CX, 37)
    	ROUND2(CX, DX, BP, AX, BX, 38)
    	ROUND2(BX, CX, DX, BP, AX, 39)
    
    	ROUND3(AX, BX, CX, DX, BP, 40)
    	ROUND3(BP, AX, BX, CX, DX, 41)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 31.5K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	VADDPD 2032(DX), X29, X0        // 62f1950058427f
    	VADDPD 2032(DX), X1, X29        // 6261f508586a7f
    	VADDPD 2032(DX), X29, X28       // 6261950058627f
    	VADDPD 2032(DX)(AX*2), X29, X0  // 62f195005844427f
    	VADDPD 2032(DX)(AX*2), X1, X29  // 6261f508586c427f
    	VADDPD 2032(DX)(AX*2), X29, X28 // 626195005864427f
    	VADDPD 4064(DX), Y0, Y29        // 6261fd28586a7f
    	VADDPD 4064(DX), Y29, Y1        // 62f19520584a7f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 57.6K bytes
    - Viewed (0)
  8. src/runtime/sys_windows_amd64.s

    	MOVQ	m_g0(CX), DX		// g
    
    	// Layout new m scheduler stack on os stack.
    	MOVQ	SP, AX
    	MOVQ	AX, (g_stack+stack_hi)(DX)
    	SUBQ	$(64*1024), AX		// initial stack size (adjusted later)
    	MOVQ	AX, (g_stack+stack_lo)(DX)
    	ADDQ	$const_stackGuard, AX
    	MOVQ	AX, g_stackguard0(DX)
    	MOVQ	AX, g_stackguard1(DX)
    
    	// Set up tls.
    	LEAQ	m_tls(CX), DI
    	MOVQ	CX, g_m(DX)
    	MOVQ	DX, g(DI)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Feb 19 07:24:08 UTC 2024
    - 8.4K bytes
    - Viewed (0)
  9. src/internal/runtime/atomic/atomic_386.s

    	MOVL	val+4(FP), CX
    casloop:
    	MOVL 	CX, DX
    	MOVL	(BX), AX
    	ANDL	AX, DX
    	LOCK
    	CMPXCHGL	DX, (BX)
    	JNZ casloop
    	MOVL 	AX, ret+8(FP)
    	RET
    
    // func Or32(addr *uint32, v uint32) old uint32
    TEXT ·Or32(SB), NOSPLIT, $0-12
    	MOVL	ptr+0(FP), BX
    	MOVL	val+4(FP), CX
    casloop:
    	MOVL 	CX, DX
    	MOVL	(BX), AX
    	ORL	AX, DX
    	LOCK
    	CMPXCHGL	DX, (BX)
    	JNZ casloop
    	MOVL 	AX, ret+8(FP)
    	RET
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 6.5K bytes
    - Viewed (0)
  10. src/cmd/internal/notsha256/sha256block_386.s

    	MOVL	((index-2)*4)(BP), AX; \
    	MOVL	AX, CX; \
    	RORL	$17, AX; \
    	MOVL	CX, DX; \
    	RORL	$19, CX; \
    	SHRL	$10, DX; \
    	MOVL	((index-15)*4)(BP), BX; \
    	XORL	CX, AX; \
    	MOVL	BX, CX; \
    	XORL	DX, AX; \
    	RORL	$7, BX; \
    	MOVL	CX, DX; \
    	SHRL	$3, DX; \
    	RORL	$18, CX; \
    	ADDL	((index-7)*4)(BP), AX; \
    	XORL	CX, BX; \
    	XORL	DX, BX; \
    	ADDL	((index-16)*4)(BP), BX; \
    	ADDL	BX, AX; \
    	MOVL	AX, ((index)*4)(BP)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:27 UTC 2023
    - 8.2K bytes
    - Viewed (0)
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