{name: "UBFIZ", argLength: 1, reg: gp11, asm: "UBFIZ", aux: "ARM64BitField"},
		// extract width bits of arg0 starting at bit lsb and insert at low end of result, remaining high bits are zeroed
		{name: "UBFX", argLength: 1, reg: gp11, asm: "UBFX", aux: "ARM64BitField"},

		// moves
		{name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "UInt64", rematerializeable: true},      // 64 bits from auxint

	ANDS R17<<11, R24, ZR                      // 1f2f11ea
	UBFIZW $3, R19, $14, R14                   // 6e361d53
	UBFIZ $3, R22, $14, R4                     // c4367dd3
	UBFXW $3, R7, $20, R15                     // ef580353
	UBFX $33, R17, $25, R5                     // 25e661d3
	UDIVW R8, R21, R15                         // af0ac81a
	UDIV R2, R19, R21                          // 750ac29a
	UMADDL R0, R20, R17, R17                   // 3152a09b

{"Name":"UBFM","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},

(RotateLeft32 x y) => (SRR x (RSBconst [0] <y.Type> y))

// ((x>>8) | (x<<8)) -> (REV16 x), the type of x is uint16, "|" can also be "^" or "+".
// UBFX instruction is supported by ARMv6T2, ARMv7 and above versions, REV16 is supported by
// ARMv6 and above versions. So for ARMv6, we need to match SLLconst, SRLconst and ORshiftLL.

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UBFX",
		auxType: auxARM64BitField,
		argLen:  1,
		asm:     arm64.AUBFX,
		reg: regInfo{
			inputs: []inputInfo{