// Act
        byte[] r14 = NtlmUtil.getPreNTLMResponse(cifsContext, password14, challenge);
        byte[] r15 = NtlmUtil.getPreNTLMResponse(cifsContext, password15, challenge);

        // Assert: equal because only first 14 OEM bytes are used
        assertArrayEquals(r14, r15, "Only first 14 OEM bytes affect Pre-NTLM response");
        assertEquals(24, r14.length);

        // Verify collaborator interactions

	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

<code>&gt;&gt;</code> (logical right shift), and
<code>@&gt;</code> (rotate right).

</li>

<li>
<code>[R0,g,R12-R15]</code>: For multi-register instructions, the set comprising
<code>R0</code>, <code>g</code>, and <code>R12</code> through <code>R15</code> inclusive.
</li>

<li>
<code>(R5, R6)</code>: Destination register pair.
</li>

</ul>

<h3 id="arm64">ARM64</h3>

	VBROADCASTF32X4 (CX), K1, Y24                      // 62627d291a01
	VBROADCASTF32X4 99(R15), K1, Y24                   // 62427d291a8763000000
	VBROADCASTF32X4 99(R15)(R15*2), K2, Z12            // 62127d4a1aa47f63000000
	VBROADCASTF32X4 -7(DI), K2, Z12                    // 62727d4a1aa7f9ffffff
	VBROADCASTF32X4 99(R15)(R15*2), K2, Z16            // 62827d4a1a847f63000000

	VMOVDQU16 Z8, K4, (CX)                             // 6271ff4c7f01
	VMOVDQU16 Z6, K4, 99(R15)                          // 62d1ff4c7fb763000000
	VMOVDQU16 Z8, K4, 99(R15)                          // 6251ff4c7f8763000000
	VMOVDQU16 Z12, K1, Z25                             // 6211ff497fe1
	VMOVDQU16 Z17, K1, Z25                             // 6281ff497fc9
	VMOVDQU16 99(R15)(R15*2), K1, Z25                  // 6201ff496f8c7f63000000

	VAESDEC 99(R15)(R15*1), Y0, Y23                    // 62827d28debc3f63000000 or 6282fd28debc3f63000000
	VAESDEC (DX), Y0, Y23                              // 62e27d28de3a or 62e2fd28de3a
	VAESDEC Z27, Z3, Z11                               // 62126548dedb or 6212e548dedb
	VAESDEC Z15, Z3, Z11                               // 62526548dedf or 6252e548dedf

	VPOPCNTB -15(R14)(R15*2), K4, Y24                  // 62027d2c54847ef1ffffff
	VPOPCNTB Y14, K4, Y13                              // 62527d2c54ee
	VPOPCNTB Y21, K4, Y13                              // 62327d2c54ed
	VPOPCNTB Y1, K4, Y13                               // 62727d2c54e9
	VPOPCNTB 15(R8)(R14*8), K4, Y13                    // 62127d2c54acf00f000000
	VPOPCNTB -15(R14)(R15*2), K4, Y13                  // 62127d2c54ac7ef1ffffff

	VANDNPD 99(R15)(R15*8), Y12, K5, Y0                // 62919d2d5584ff63000000
	VANDNPD 7(AX)(CX*8), Y12, K5, Y0                   // 62f19d2d5584c807000000
	VANDNPD Y17, Y1, K5, Y0                            // 62b1f52d55c1
	VANDNPD Y7, Y1, K5, Y0                             // 62f1f52d55c7
	VANDNPD Y9, Y1, K5, Y0                             // 62d1f52d55c1

	VPOPCNTQ 99(R15)(R15*4), K4, X23                   // 6282fd0c55bcbf63000000
	VPOPCNTQ 15(DX), K4, X23                           // 62e2fd0c55ba0f000000
	VPOPCNTQ X24, K4, X11                              // 6212fd0c55d8
	VPOPCNTQ X14, K4, X11                              // 6252fd0c55de
	VPOPCNTQ X0, K4, X11                               // 6272fd0c55d8
	VPOPCNTQ 99(R15)(R15*4), K4, X11                   // 6212fd0c559cbf63000000

	VPCONFLICTQ 99(R15)(R15*8), K4, Y24                // 6202fd2cc484ff63000000
	VPCONFLICTQ 7(AX)(CX*8), K4, Y24                   // 6262fd2cc484c807000000
	VPCONFLICTQ Y5, K4, Y1                             // 62f2fd2cc4cd
	VPCONFLICTQ Y18, K4, Y1                            // 62b2fd2cc4ca
	VPCONFLICTQ Y20, K4, Y1                            // 62b2fd2cc4cc
	VPCONFLICTQ 99(R15)(R15*8), K4, Y1                 // 6292fd2cc48cff63000000