// Non-X0 for Yxr0 should produce an error
	BLENDVPD X1, (BX), X2           // ERROR "invalid instruction"
	// Check offset overflow. Must fit in int32.
	MOVQ 2147483647+1(AX), AX       // ERROR "offset too large"
	MOVQ 3395469782(R10), R8        // ERROR "offset too large"
	LEAQ 3395469782(AX), AX         // ERROR "offset too large"
	ADDQ 3395469782(AX), AX         // ERROR "offset too large"
	ADDL 3395469782(AX), AX         // ERROR "offset too large"

</p>

<h3 id="arm">ARM</h3>

<p>
The registers <code>R10</code> and <code>R11</code>
are reserved by the compiler and linker.
</p>

<p>
<code>R10</code> points to the <code>g</code> (goroutine) structure.
Within assembler source code, this pointer must be referred to as <code>g</code>;
the name <code>R10</code> is not recognized.
</p>

<p>

	// Note that there is no list of names as there is for x86.
	for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	// Avoid unintentionally clobbering g using R10.
	delete(register, "R10")
	register["g"] = arm.REG_R10
	for i := 0; i < 16; i++ {
		register[fmt.Sprintf("C%d", i)] = int16(i)
	}

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP

	p.expectOperandEnd()
	return
}

// atStartOfRegister reports whether the parser is at the start of a register definition.
func (p *Parser) atStartOfRegister(name string) bool {
	// Simple register: R10.
	_, present := p.arch.Register[name]
	if present {
		return true
	}
	// Parenthesized register: R(10).
	return p.arch.RegisterPrefix[name] && p.peek() == '('
}

TEXT asmtest_avx512pf(SB), NOSPLIT, $0
	VGATHERPF0DPD K5, (R10)(Y29*8)                     // 6292fd45c60cea
	VGATHERPF0DPD K5, (SP)(Y4*2)                       // 62f2fd4dc60c64
	VGATHERPF0DPD K5, (DX)(Y10*4)                      // 62b2fd4dc60c92
	VGATHERPF0DPS K3, (BP)(Z10*2)                      // 62b27d4bc64c5500
	VGATHERPF0DPS K3, (R10)(Z29*8)                     // 62927d43c60cea

		Type:  obj.TYPE_BRANCH,
		Index: 0,
	}
	addr.Val = target
}

func isARM64SVE(op obj.As) bool {
	return op > arm64.ASVESTART
}

// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
	// fmt.Printf("%s %+v\n", op, a)
	prog := &obj.Prog{
		Ctxt: p.ctxt,
		Pos:  p.pos(),
		As:   op,
	}
	switch len(a) {
	case 0:

	VCVTSS2USIQ X19, BP                                // 62b1fe0879eb
	VCVTSS2USIQ X13, R10                               // 6251fe0879d5 or 6251fe2879d5 or 6251fe4879d5
	VCVTSS2USIQ -17(BP)(SI*2), R10                     // 6271fe08799475efffffff or 6271fe28799475efffffff or 6271fe48799475efffffff
	VCVTSS2USIQ 7(AX)(CX*2), R10                       // 6271fe0879944807000000 or 6271fe2879944807000000 or 6271fe4879944807000000

	KMOVQ 7(AX), K5                                    // c4e1f8906807
	KMOVQ (DI), K5                                     // c4e1f8902f
	KMOVQ R10, K3                                      // c4c1fb92da
	KMOVQ CX, K3                                       // c4e1fb92d9
	KMOVQ R10, K1                                      // c4c1fb92ca
	KMOVQ CX, K1                                       // c4e1fb92c9

pkg debug/macho, type RegsAMD64 struct, FS uint64
pkg debug/macho, type RegsAMD64 struct, GS uint64
pkg debug/macho, type RegsAMD64 struct, IP uint64
pkg debug/macho, type RegsAMD64 struct, R10 uint64
pkg debug/macho, type RegsAMD64 struct, R11 uint64
pkg debug/macho, type RegsAMD64 struct, R12 uint64
pkg debug/macho, type RegsAMD64 struct, R13 uint64
pkg debug/macho, type RegsAMD64 struct, R14 uint64