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Results 11 - 20 of 25 for ORN (0.04 sec)
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src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "ORNshiftLL", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64"}, // arg0 | ^(arg1<<auxInt), auxInt should be in the range 0 to 63. {name: "ORNshiftRL", argLength: 2, reg: gp21, asm: "ORN", aux: "Int64"}, // arg0 | ^(arg1>>auxInt), unsigned shift, auxInt should be in the range 0 to 63.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
SUBFZE: "SUBZE", SUBFZECC: "SUBZECC", SUBFZEO: "SUBZEV", SUBFZEOCC: "SUBZEVCC", SUBF: "SUB", SUBFC: "SUBC", SUBFCC: "SUBCC", SUBFCCC: "SUBCCC", ORC: "ORN", ORCCC: "ORNCC", MULLWO: "MULLWV", MULLWOCC: "MULLWVCC", MULLDO: "MULLDV", MULLDOCC: "MULLDVCC", DIVDO: "DIVDV", DIVDOCC: "DIVDVCC", DIVDUO: "DIVDUV",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go
// ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount> } {0xff208000, 0x2a200000, ORN, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, // MVN <Xd>, <Xm> {, <shift> #<amount> } {0xff2003e0, 0xaa2003e0, MVN, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, // ORN <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 211.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(BIC x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (BICshiftRO x0 y [c]) (ORN x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ORNshiftLL x0 y [c]) (ORN x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ORNshiftRL x0 y [c]) (ORN x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ORNshiftRA x0 y [c]) (ORN x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ORNshiftRO x0 y [c])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// Catch bounded shifts in situations like foo<<uint(shift&63) which might not be caught by the prove pass. (CMP(U|WU)const [d] (ANDconst z [c])) && uint64(d) > uint64(c) => (FlagLT) (ORN x (MOVDconst [-1])) => x (S(RAD|RD|LD) x (MOVDconst [c])) => (S(RAD|RD|LD)const [c&63 | (c>>6&1*63)] x) (S(RAW|RW|LW) x (MOVDconst [c])) => (S(RAW|RW|LW)const [c&31 | (c>>5&1*31)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
EOR $0x22220000, R3, R4 // EOR $572653568, R3, R4 // 5b44a4d264001bca BIC $0x22220000, R3, R4 // BIC $572653568, R3, R4 // 5b44a4d264003b8a ORN $0x22220000, R3, R4 // ORN $572653568, R3, R4 // 5b44a4d264003baa EON $0x22220000, R3, R4 // EON $572653568, R3, R4 // 5b44a4d264003bca
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 94.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 234.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
NGCSW R10, R5 // e5030a7a NGCS R24, R16 // f00318fa NOOP // 1f2003d5 ORNW R4@>11, R16, R3 // 032ee42a ORN R22@>19, R3, R3 // 634cf6aa ORRW $4294443071, R15, R24 // f8490d32 ORR $-3458764513820540929, R12, R22 // 96f542b2 ORRW R13<<4, R8, R26 // 1a110d2a
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
case lex.LSH: op = 0 case lex.RSH: op = 1 case lex.ARR: op = 2 case lex.ROT: // following instructions on ARM64 support rotate right // AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN op = 3 } tok := p.next() str := tok.String() var count int16 switch tok.ScanToken { case scanner.Ident: if p.arch.Family == sys.ARM64 { p.errorf("rhs of shift must be integer: %s", str)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 21 14:34:57 UTC 2024 - 36.9K bytes - Viewed (0)