MSR_EQ:            "MSR.EQ",
	MSR_NE:            "MSR.NE",
	MSR_CS:            "MSR.CS",
	MSR_CC:            "MSR.CC",
	MSR_MI:            "MSR.MI",
	MSR_PL:            "MSR.PL",
	MSR_VS:            "MSR.VS",
	MSR_VC:            "MSR.VC",
	MSR_HI:            "MSR.HI",
	MSR_LS:            "MSR.LS",
	MSR_GE:            "MSR.GE",
	MSR_LT:            "MSR.LT",
	MSR_GT:            "MSR.GT",

	SizeofMsghdr          = 0x38
	SizeofCmsghdr         = 0x10
)

const (
	SizeofSockFprog = 0x10
)

type PtraceRegs struct {
	Gpr       [32]uint64
	Nip       uint64
	Msr       uint64
	Orig_gpr3 uint64
	Ctr       uint64
	Link      uint64
	Xer       uint64
	Ccr       uint64
	Softe     uint64
	Trap      uint64
	Dar       uint64
	Dsisr     uint64
	Result    uint64

	SizeofMsghdr          = 0x1c
	SizeofCmsghdr         = 0xc
)

const (
	SizeofSockFprog = 0x8
)

type PtraceRegs struct {
	Gpr       [32]uint32
	Nip       uint32
	Msr       uint32
	Orig_gpr3 uint32
	Ctr       uint32
	Link      uint32
	Xer       uint32
	Ccr       uint32
	Mq        uint32
	Trap      uint32
	Dar       uint32
	Dsisr     uint32
	Result    uint32

	SizeofMsghdr          = 0x38
	SizeofCmsghdr         = 0x10
)

const (
	SizeofSockFprog = 0x10
)

type PtraceRegs struct {
	Gpr       [32]uint64
	Nip       uint64
	Msr       uint64
	Orig_gpr3 uint64
	Ctr       uint64
	Link      uint64
	Xer       uint64
	Ccr       uint64
	Softe     uint64
	Trap      uint64
	Dar       uint64
	Dsisr     uint64
	Result    uint64

	// MRS <Xt>, <systemreg>
	{0xfff00000, 0xd5300000, MRS, instArgs{arg_Xt, arg_sysreg_o0_op1_CRn_CRm_op2}, nil},
	// MSR <pstatefield>, #<imm>
	{0xfff8f01f, 0xd500401f, MSR, instArgs{arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37, arg_immediate_0_15_CRm}, nil},
	// MSR <systemreg>, <Xt>
	{0xfff00000, 0xd5100000, MSR, instArgs{arg_sysreg_o0_op1_CRn_CRm_op2, arg_Xt}, nil},
	// MVN <Wd>, <Wm> {, <shift> #<amount> }

	}
	register["CR"] = ppc64.REG_CR
	register["XER"] = ppc64.REG_XER
	register["LR"] = ppc64.REG_LR
	register["CTR"] = ppc64.REG_CTR
	register["FPSCR"] = ppc64.REG_FPSCR
	register["MSR"] = ppc64.REG_MSR
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	// Avoid unintentionally clobbering g using R30.
	delete(register, "R30")
	register["g"] = ppc64.REG_R30

			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[0], args[1] = args[1], args[0]

	case ADR, ADRP:
		addr := int64(inst.Args[1].(PCRel))
		args[1] = fmt.Sprintf("%d(PC)", addr)

	case MSR:
		args[0] = inst.Args[0].String()

	case ST1:
		op = fmt.Sprintf("V%s", op) + suffix
		args[0], args[1] = args[1], args[0]

	case LD1:
		op = fmt.Sprintf("V%s", op) + suffix

	case UMOV:

done:
	MOVL	AX, ret_lo+0(FP)
	MOVL	DX, ret_hi+4(FP)
	RET
fences:
	// MFENCE is instruction stream serializing and flushes the
	// store buffers on AMD. The serialization semantics of LFENCE on AMD
	// are dependent on MSR C001_1029 and CPU generation.
	// LFENCE on Intel does wait for all previous instructions to have executed.
	// Intel recommends MFENCE;LFENCE in its manuals before RDTSC to have all

{"Name":"MSR (immediate)","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|op1:3|0|1|0|0|CRm:4|op2:3|1|1|1|1|1","Arch":"System variant","Syntax":"MSR <pstatefield>, #<imm>","Code":"","Alias":""},
{"Name":"MSR (register)","Bits":"1|1|0|1|0|1|0|1|0|0|0|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MSR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>","Code":"","Alias":""},

		}
		if (o1 & (v &^ (3 << 19))) != 0 {
			c.ctxt.Diag("MSR register value overlap\n%v", p)
		}
		if accessFlags&SR_WRITE == 0 {
			c.ctxt.Diag("system register is not writable: %v", p)
		}

		o1 |= v
		o1 |= uint32(p.From.Reg & 31)

	case 37: /* mov $con,PSTATEfield -> MSR [immediate] */
		if (uint64(p.From.Offset) &^ uint64(0xF)) != 0 {