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src/cmd/asm/internal/asm/testdata/arm64enc.s
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Feb 24 21:29:25 GMT 2026 - 44K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
MOV $8(SP), (X5) // ERROR "address load must target register" MOVB $8(SP), X5 // ERROR "unsupported address load" MOVH $8(SP), X5 // ERROR "unsupported address load" MOVW $8(SP), X5 // ERROR "unsupported address load" MOVF $8(SP), X5 // ERROR "unsupported address load" MOV $1234, 0(SP) // ERROR "constant load must target register"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Apr 01 04:17:57 GMT 2026 - 27.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
//TODO: MOVW DS, (R11) // 66418c1b or 498c1b //TODO: MOVW SS, DX // 668cd2 or 488cd2 //TODO: MOVW DS, DX // 668cda or 488cda //TODO: MOVW SS, R11 // 66418cd3 or 498cd3 //TODO: MOVW DS, R11 // 66418cdb or 498cdb MOVW $61731, (BX) // 66c70323f1 MOVW $61731, (R11) // 6641c70323f1
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Oct 08 21:38:44 GMT 2021 - 581.9K bytes - Click Count (1) -
src/cmd/asm/internal/asm/testdata/riscv64.s
MOVH (X5), X6 // 03930200 MOVH 4(X5), X6 // 03934200 MOVW (X5), X6 // 03a30200 MOVW 4(X5), X6 // 03a34200 MOV X5, (X6) // 23305300 MOV X5, 4(X6) // 23325300 MOVB X5, (X6) // 23005300 MOVB X5, 4(X6) // 23025300 MOVH X5, (X6) // 23105300 MOVH X5, 4(X6) // 23125300 MOVW X5, (X6) // 23205300 MOVW X5, 4(X6) // 23225300
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0) -
lib/fips140/v1.26.0.zip
R8, R9) SHA256ROUND1(63, R9, R10, R11, R12, R13, R14, R15, R8) MOVW (0*4)(R4), REGTMP MOVW (1*4)(R4), REGTMP1 MOVW (2*4)(R4), REGTMP2 MOVW (3*4)(R4), REGTMP3 ADD REGTMP, R8 // H0 = a + H0 ADD REGTMP1, R9 // H1 = b + H1 ADD REGTMP2, R10 // H2 = c + H2 ADD REGTMP3, R11 // H3 = d + H3 MOVW R8, (0*4)(R4) MOVW R9, (1*4)(R4) MOVW R10, (2*4)(R4) MOVW R11, (3*4)(R4) MOVW (4*4)(R4), REGTMP MOVW (5*4)(R4), REGTMP1 MOVW (6*4)(R4), REGTMP2 MOVW (7*4)(R4), REGTMP3 ADD REGTMP, R12 // H4 = e + H4 ADD REGTMP1, R13...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Jan 08 17:58:32 GMT 2026 - 660.3K bytes - Click Count (0) -
doc/asm.html
</p> <p> Instruction modifiers are appended to the instruction following a period. The only modifiers are <code>P</code> (postincrement) and <code>W</code> (preincrement): <code>MOVW.P</code>, <code>MOVW.W</code> </p> <p> Addressing modes: </p> <ul> <li> <code>R0->16</code> <br> <code>R0>>16</code> <br> <code>R0<<16</code> <br>
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Nov 14 19:09:46 GMT 2025 - 36.5K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
SHA256ROUND1(63, 0xc67178f2, R9, R10, R11, R12, R13, R14, R15, R8) MOVW (0*4)(R4), REGTMP MOVW (1*4)(R4), REGTMP1 MOVW (2*4)(R4), REGTMP2 MOVW (3*4)(R4), REGTMP3 ADD REGTMP, R8 // H0 = a + H0 ADD REGTMP1, R9 // H1 = b + H1 ADD REGTMP2, R10 // H2 = c + H2 ADD REGTMP3, R11 // H3 = d + H3 MOVW R8, (0*4)(R4) MOVW R9, (1*4)(R4) MOVW R10, (2*4)(R4) MOVW R11, (3*4)(R4) MOVW (4*4)(R4), REGTMP MOVW (5*4)(R4), REGTMP1 MOVW (6*4)(R4), REGTMP2 MOVW (7*4)(R4), REGTMP3 ADD REGTMP, R12 // H4 = e + H4 ADD REGTMP1, R13...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0)