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Results 1 - 5 of 5 for SXTW (0.07 sec)
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src/cmd/asm/internal/asm/testdata/arm64enc.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
MOVW R8, (R2)(R3.UXTW<<2) // 485823b8 MOVW R7, (R3)(R4.SXTW) // 67c824b8 MOVB R4, (R2)(R6.SXTX) // 44e82638 MOVB R8, (R3)(R9.UXTW) // 68482938 MOVB R10, (R5)(R8) // aa682838 MOVB R10, (R5)(R8*1) // aa682838 MOVH R11, (R2)(R7.SXTW<<1) // 4bd82778 MOVH R5, (R1)(R2<<1) // 25782278
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jul 24 18:45:14 UTC 2024 - 95.2K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
} a.Reg = arm64.REG_SXTB + Rnum case "SXTH": if a.Type == obj.TYPE_MEM { return errors.New("invalid shift for the register offset addressing mode") } a.Reg = arm64.REG_SXTH + Rnum case "SXTW": if a.Type == obj.TYPE_MEM { a.Index = arm64.REG_SXTW + Rnum } else { a.Reg = arm64.REG_SXTW + Rnum } case "SXTX": if a.Type == obj.TYPE_MEM { a.Index = arm64.REG_SXTX + Rnum
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Sep 29 09:04:58 UTC 2022 - 10.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 37.8K bytes - Viewed (0) -
doc/asm.html
<code>R0.SXTB<<imm</code>: left shift the result of <code>R0.SXTB</code> by <code>imm</code> bits. The <code>imm</code> value can be 0, 1, 2, 3, or 4. The other extensions include <code>SXTH</code> (16-bit), <code>SXTW</code> (32-bit), and <code>SXTX</code> (64-bit). </li> <li> <code>(R5, R6)</code>: Register pair for <code>LDAXP</code>/<code>LDP</code>/<code>LDXP</code>/<code>STLXP</code>/<code>STP</code>/<code>STP</code>. </li>
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0)