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Results 1 - 7 of 7 for SLLVconst (0.41 sec)
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src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr) (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))) (NORconst [0] <typ.UInt64> (SLLV <typ.UInt64> (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))))) mem) // AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0]) (SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0]) (SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63]) (SLLV x (MOVVconst [c])) => (SLLVconst x [c]) (SRLV x (MOVVconst [c])) => (SRLVconst x [c]) (SRAV x (MOVVconst [c])) => (SRAVconst x [c]) (ROTR x (MOVVconst [c])) => (ROTRconst x [c&31]) (ROTRV x (MOVVconst [c])) => (ROTRVconst x [c&63])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteMIPS64.go
// cond: !config.BigEndian // result: (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr) (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))) (NORconst [0] <typ.UInt64> (SLLV <typ.UInt64> (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))))) mem) for { ptr := v_0 val := v_1 mem := v_2 if !(!config.BigEndian) { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 211.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
{name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 // shifts {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64 {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt {name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteLOONG64.go
continue } v.copyOf(x) return true } break } // match: (MULV x (MOVVconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLVconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpLOONG64MOVVconst { continue } c := auxIntToInt64(v_1.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 195.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)