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Results 11 - 20 of 22 for rldic (0.07 sec)
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pkg/registry/admissionregistration/validatingwebhookconfiguration/strategy.go
newIC := obj.(*admissionregistration.ValidatingWebhookConfiguration) oldIC := old.(*admissionregistration.ValidatingWebhookConfiguration) // Any changes to the spec increment the generation number, any changes to the // status should reflect the generation number of the corresponding object. // See metav1.ObjectMeta description for more information on Generation. if !reflect.DeepEqual(oldIC.Webhooks, newIC.Webhooks) { newIC.Generation = oldIC.Generation + 1
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Thu Feb 29 20:14:19 UTC 2024 - 4.1K bytes - Viewed (0) -
pkg/registry/admissionregistration/mutatingwebhookconfiguration/strategy.go
newIC := obj.(*admissionregistration.MutatingWebhookConfiguration) oldIC := old.(*admissionregistration.MutatingWebhookConfiguration) // Any changes to the spec increment the generation number, any changes to the // status should reflect the generation number of the corresponding object. // See metav1.ObjectMeta description for more information on Generation. if !reflect.DeepEqual(oldIC.Webhooks, newIC.Webhooks) { newIC.Generation = oldIC.Generation + 1
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Thu Feb 29 20:14:19 UTC 2024 - 4K bytes - Viewed (0) -
pkg/registry/admissionregistration/validatingadmissionpolicy/strategy.go
newIC := obj.(*admissionregistration.ValidatingAdmissionPolicy) oldIC := old.(*admissionregistration.ValidatingAdmissionPolicy) // Prevent any update on the Spec object from Status Strategy newIC.Spec = oldIC.Spec metav1.ResetObjectMetaForStatus(&newIC.ObjectMeta, &oldIC.ObjectMeta) // No change in the generation. }
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Wed Mar 06 00:00:21 UTC 2024 - 7.8K bytes - Viewed (0) -
test/codegen/arithmetic.go
// arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" a := n1%64 == 0 // signed divisible // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" b := n2%64 != 0 // signed indivisible return a, b }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
src/vendor/golang.org/x/crypto/internal/poly1305/sum_ppc64le.s
MULLD h2, r1, t3; \ ADDZE t4, h0; \ MULHDU r1, h1, t5; \ MULLD r1, h1, t4; \ ADDC t4, t2, t2; \ ADDE t5, t3, t3; \ ADDC h0, t2, t2; \ MOVD $-4, t4; \ ADDZE t3; \ RLDICL $0, t2, $62, h2; \ AND t2, t4, h0; \ ADDC t0, h0, h0; \ ADDE t3, t1, h1; \ SLD $62, t3, t4; \ SRD $2, t2; \ ADDZE h2; \ OR t4, t2, t2; \ SRD $2, t3; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Mar 09 00:09:40 UTC 2024 - 3.2K bytes - Viewed (0) -
src/runtime/sys_linux_ppc64x.s
MOVD m_curg(R21), R6 CMP g, R6 BNE noswitch MOVD m_g0(R21), R7 MOVD (g_sched+gobuf_sp)(R7), R1 // Set SP to g0 stack noswitch: SUB $16, R1 // Space for results RLDICR $0, R1, $59, R1 // Align for C code MOVD R12, CTR MOVD R1, R4 // Store g on gsignal's stack, so if we receive a signal // during VDSO code we can find the g.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 18.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
} // Merge (RLDICL [encoded] (SRDconst [s] x)) into (RLDICL [new_encoded] x) // SRDconst on PPC64 is an extended mnemonic of RLDICL. If the input to an // RLDICL is an SRDconst, and the RLDICL does not rotate its value, the two // operations can be combined. This functions assumes the two opcodes can // be merged, and returns an encoded rotate+mask value of the combined RLDICL.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
AMULLDVCC AMULLDV ARFID ARLDMI ARLDMICC ARLDIMI ARLDIMICC ARLDC ARLDCCC ARLDCR ARLDCRCC ARLDICR ARLDICRCC ARLDCL ARLDCLCC ARLDICL ARLDICLCC ARLDIC ARLDICCC ACLRLSLDI AROTL AROTLW ASLBIA ASLBIE ASLBMFEE ASLBMFEV ASLBMTE ASLD ASLDCC ASRD ASRAD ASRADCC ASRDCC AEXTSWSLI AEXTSWSLICC
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/mdo/reader-stax.vm
entities.put("ni", "\u220b"); entities.put("prod", "\u220f"); entities.put("sum", "\u2211"); entities.put("minus", "\u2212"); entities.put("lowast", "\u2217"); entities.put("radic", "\u221a"); entities.put("prop", "\u221d"); entities.put("infin", "\u221e"); entities.put("ang", "\u2220"); entities.put("and", "\u2227"); entities.put("or", "\u2228");
Registered: Wed Jun 12 09:55:16 UTC 2024 - Last Modified: Mon Mar 25 10:50:01 UTC 2024 - 38.1K bytes - Viewed (0)