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Results 51 - 60 of 70 for r23 (0.02 sec)
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src/runtime/signal_linux_mipsx.go
func (c *sigctxt) r21() uint32 { return uint32(c.regs().sc_regs[21]) } func (c *sigctxt) r22() uint32 { return uint32(c.regs().sc_regs[22]) } func (c *sigctxt) r23() uint32 { return uint32(c.regs().sc_regs[23]) } func (c *sigctxt) r24() uint32 { return uint32(c.regs().sc_regs[24]) } func (c *sigctxt) r25() uint32 { return uint32(c.regs().sc_regs[25]) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 28 18:17:57 UTC 2021 - 3.7K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
SLD $2,R19,R19 // p[5]*4:1 MOVWZ (R10)(R18),R22 // tab[1][p[6]] ADD $1024,R10,R10 // tab[2] XOR R21,R22,R21 // xor done R22 CLRLSLDI $56,R9,$2,R20 MOVWZ (R10)(R19),R23 // tab[2][p[5]] ADD $1024,R10,R10 // &tab[3] XOR R21,R23,R21 // xor done R23 MOVWZ (R10)(R20),R24 // tab[3][p[4]] ADD $1024,R10,R10 // &tab[4] XOR R21,R24,R21 // xor done R24 MOVWZ (R10)(R8),R25 // tab[4][crc>>24] RLDICL $48,R7,$56,R24 // crc>>16&0xFF
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/runtime/asm_ppc64x.s
XOR R0, R0 CMP R22, $0 BEQ good MOVD 48(R1), R22 MOVD $8, R20 TW $31, R0, R0 BR restore good: #define DEBUG_CALL_DISPATCH(NAME,MAXSIZE) \ MOVD $MAXSIZE, R23; \ CMP R26, R23; \ BGT 5(PC); \ MOVD $NAME(SB), R26; \ MOVD R26, 32(R1); \ CALL runtime·debugCallWrap(SB); \ BR restore // the argument frame size MOVD 128(R1), R26
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 45.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
// Upper bytes are junk. // - *const instructions may use a constant larger than the instruction can encode. // In this case the assembler expands to multiple instructions and uses tmp // register (R23). // Suffixes encode the bit width of various instructions. // V (vlong) = 64 bit // WU (word) = 32 bit unsigned // W (word) = 32 bit // H (half word) = 16 bit // HU = 16 bit unsigned
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/crypto/md5/md5block_ppc64x.s
#define M02 R20 #define M03 R24 #define M04 R25 #define M05 R26 #define M06 R27 #define M07 R28 #define M08 R29 #define M09 R21 #define M10 R11 #define M11 R8 #define M12 R7 #define M13 R12 #define M14 R23 #define M15 R10 #define ROUND1(a, b, c, d, index, const, shift) \ ADD $const, index, R9; \ ADD R9, a; \ AND b, c, R9; \ ANDN b, d, R31; \ OR R9, R31, R9; \ ADD R9, a; \ ROTLW $shift, a; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 18:05:32 UTC 2024 - 5.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
// - *const instructions may use a constant larger than the instruction can encode. // In this case the assembler expands to multiple instructions and uses tmp // register (R23). // Suffixes encode the bit width of various instructions. // W (word) = 32 bit // H (half word) = 16 bit // HU = 16 bit unsigned // B (byte) = 8 bit // BU = 8 bit unsigned
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/runtime/mkduff.go
} fmt.Fprintln(w, "\tRET") } func copyMIPS64x(w io.Writer) { fmt.Fprintln(w, "TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0") for i := 0; i < 128; i++ { fmt.Fprintln(w, "\tMOVV\t(R1), R23") fmt.Fprintln(w, "\tADDV\t$8, R1") fmt.Fprintln(w, "\tMOVV\tR23, (R2)") fmt.Fprintln(w, "\tADDV\t$8, R2") fmt.Fprintln(w) } fmt.Fprintln(w, "\tRET") } func zeroRISCV64(w io.Writer) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:21 UTC 2023 - 8K bytes - Viewed (0) -
src/runtime/asm_arm64.s
STP (R12, R13), 11*8(RSP) STP (R14, R15), 13*8(RSP) // R16, R17 may be clobbered by linker trampoline // R18 is unused. STP (R19, R20), 15*8(RSP) STP (R21, R22), 17*8(RSP) STP (R23, R24), 19*8(RSP) STP (R25, R26), 21*8(RSP) // R27 is temp register. // R28 is g. // R29 is frame pointer (unused). // R30 is LR, which was saved by the prologue. // R31 is SP.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 43.4K bytes - Viewed (0) -
src/crypto/sha512/sha512block_ppc64x.s
#define R_x030 R26 #define R_x040 R14 #define R_x050 R15 #define R_x060 R16 #define R_x070 R17 #define R_x080 R18 #define R_x090 R19 #define R_x0a0 R20 #define R_x0b0 R21 #define R_x0c0 R22 #define R_x0d0 R23 #define R_x0e0 R24 #define R_x0f0 R28 #define R_x100 R29 #define R_x110 R27 // V0-V7 are A-H // V8-V23 are used for the message schedule #define KI V24 #define FUNC V25 #define S0 V26
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 15.8K bytes - Viewed (0) -
src/crypto/sha256/sha256block_ppc64x.s
#define R_x030 R11 #define R_x040 R14 #define R_x050 R15 #define R_x060 R16 #define R_x070 R17 #define R_x080 R18 #define R_x090 R19 #define R_x0a0 R20 #define R_x0b0 R21 #define R_x0c0 R22 #define R_x0d0 R23 #define R_x0e0 R24 #define R_x0f0 R25 #define R_x100 R26 #define R_x110 R27 // V0-V7 are A-H // V8-V23 are used for the message schedule #define KI V24 #define FUNC V25 #define S0 V26
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 14.4K bytes - Viewed (0)