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Results 41 - 50 of 142 for r13 (0.05 sec)
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src/syscall/asm9_unix2_amd64.s
MOVQ a4+32(FP), R10 MOVQ a5+40(FP), R8 MOVQ a6+48(FP), R9 MOVQ a7+56(FP), R11 MOVQ a8+64(FP), R12 MOVQ a9+72(FP), R13 // only the first 6 arguments can be passed in registers, // the last three should be placed at the top of the stack. MOVQ R11, 8(SP) // arg 7 MOVQ R12, 16(SP) // arg 8 MOVQ R13, 24(SP) // arg 9 SYSCALL JCC ok9 MOVQ $-1, r1+80(FP) // r1 MOVQ $0, r2+88(FP) // r2 MOVQ AX, err+96(FP) // errno
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 16:59:50 UTC 2023 - 1.2K bytes - Viewed (0) -
test/codegen/clobberdeadreg.go
// amd64:`MOVQ\t\$-2401018187971961171, R11`, `MOVQ\t\$-2401018187971961171, R12`, `MOVQ\t\$-2401018187971961171, R13` // amd64:-`MOVQ\t\$-2401018187971961171, BP` // frame pointer is not clobbered StackArgsCall([10]int{a, b, c}) // amd64:`MOVQ\t\$-2401018187971961171, R12`, `MOVQ\t\$-2401018187971961171, R13`, `MOVQ\t\$-2401018187971961171, DX`
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:25 UTC 2023 - 1.3K bytes - Viewed (0) -
src/runtime/cgo/gcc_amd64.S
EXT(crosscall1): pushq %rbx pushq %rbp pushq %r12 pushq %r13 pushq %r14 pushq %r15 #if defined(_WIN64) movq %r8, %rdi /* arg of setg_gcc */ call *%rdx /* setg_gcc */ call *%rcx /* fn */ #else movq %rdi, %rbx movq %rdx, %rdi /* arg of setg_gcc */ call *%rsi /* setg_gcc */ call *%rbx /* fn */ #endif popq %r15 popq %r14 popq %r13 popq %r12 popq %rbp popq %rbx ret
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Aug 12 03:56:28 UTC 2023 - 1.1K bytes - Viewed (0) -
src/runtime/cgo/gcc_s390x.S
.file "gcc_s390x.S" /* * void crosscall_s390x(void (*fn)(void), void *g) * * Calling into the go tool chain, where all registers are caller save. * Called from standard s390x C ABI, where r6-r13, r15, and f8-f15 are * callee-save, so they must be saved explicitly. */ .globl crosscall_s390x crosscall_s390x: /* save r6-r15 in the register save area of the calling function */ stmg %r6, %r15, 48(%r15)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Dec 05 16:41:48 UTC 2022 - 1.4K bytes - Viewed (0) -
src/runtime/preempt_amd64.s
MOVQ AX, 0(SP) MOVQ CX, 8(SP) MOVQ DX, 16(SP) MOVQ BX, 24(SP) MOVQ SI, 32(SP) MOVQ DI, 40(SP) MOVQ R8, 48(SP) MOVQ R9, 56(SP) MOVQ R10, 64(SP) MOVQ R11, 72(SP) MOVQ R12, 80(SP) MOVQ R13, 88(SP) MOVQ R14, 96(SP) MOVQ R15, 104(SP) #ifdef GOOS_darwin #ifndef hasAVX CMPB internal∕cpu·X86+const_offsetX86HasAVX(SB), $0 JE 2(PC) #endif VZEROUPPER #endif MOVUPS X0, 112(SP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Aug 18 17:17:01 UTC 2022 - 1.7K bytes - Viewed (0) -
src/runtime/race_arm64.s
// load_g will clobber R0, Save R0 MOVD R0, R13 load_g // restore R0 MOVD R13, R0 MOVD g_m(g), R13 MOVD m_g0(R13), R14 CMP R14, g BEQ noswitch // branch if already on g0 MOVD R14, g MOVD R0, 8(RSP) // func arg MOVD R1, 16(RSP) // func arg BL runtime·racecallback(SB) // All registers are smashed after Go code, reload. MOVD g_m(g), R13 MOVD m_curg(R13), g // g = m->curg ret:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 18:37:29 UTC 2024 - 15.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/plan9x.go
R8L: "R8", R9L: "R9", R10L: "R10", R11L: "R11", R12L: "R12", R13L: "R13", R14L: "R14", R15L: "R15", RAX: "AX", RCX: "CX", RDX: "DX", RBX: "BX", RSP: "SP", RBP: "BP", RSI: "SI", RDI: "DI", R8: "R8", R9: "R9", R10: "R10", R11: "R11", R12: "R12", R13: "R13", R14: "R14", R15: "R15", IP: "IP", EIP: "IP", RIP: "IP",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 12 20:38:21 UTC 2023 - 7.2K bytes - Viewed (0) -
src/internal/chacha8rand/chacha8_amd64.s
INCL CX MOVL CX, 8(SP) INCL CX MOVL CX, 12(SP) MOVOU 0(SP), X12 // Load seed words into next two rows and into DI, SI, R8..R13 SEED(0, DI, X4) SEED(1, SI, X5) SEED(2, R8, X6) SEED(3, R9, X7) SEED(4, R10, X8) SEED(5, R11, X9) SEED(6, R12, X10) SEED(7, R13, X11) // Zeros for remaining two matrix entries. // We have just enough XMM registers to hold the state,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Dec 05 20:34:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/crypto/internal/bigmod/nat_arm64.s
ADDS R4, R9 MUL R6, R3, R14 ADCS R14, R10 MUL R7, R3, R15 LDP 16(R1), (R11, R12) ADCS R15, R11 MUL R8, R3, R16 ADCS R16, R12 UMULH R8, R3, R20 ADC $0, R20 MUL R5, R3, R13 ADDS R13, R9 UMULH R5, R3, R17 ADCS R17, R10 UMULH R6, R3, R21 STP.P (R9, R10), 16(R1) ADCS R21, R11 UMULH R7, R3, R19 ADCS R19, R12 STP.P (R11, R12), 16(R1) ADC $0, R20, R4 SUB $4, R0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 22:37:58 UTC 2023 - 1.4K bytes - Viewed (0) -
src/runtime/preempt_arm64.s
#ifdef GOOS_ios MOVD R30, (RSP) #endif STP (R0, R1), 8(RSP) STP (R2, R3), 24(RSP) STP (R4, R5), 40(RSP) STP (R6, R7), 56(RSP) STP (R8, R9), 72(RSP) STP (R10, R11), 88(RSP) STP (R12, R13), 104(RSP) STP (R14, R15), 120(RSP) STP (R16, R17), 136(RSP) STP (R19, R20), 152(RSP) STP (R21, R22), 168(RSP) STP (R23, R24), 184(RSP) STP (R25, R26), 200(RSP) MOVD NZCV, R0 MOVD R0, 216(RSP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 03 01:58:56 UTC 2022 - 2K bytes - Viewed (0)