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Results 31 - 40 of 71 for auxInt8 (0.49 sec)
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src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float32", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
case ssa.OpPPC64ISEL, ssa.OpPPC64ISELZ: // ISEL AuxInt ? arg0 : arg1 // ISELZ is a special case of ISEL where arg1 is implicitly $0. // // AuxInt value indicates conditions 0=LT 1=GT 2=EQ 3=SO 4=GE 5=LE 6=NE 7=NSO. // ISEL accepts a CR bit argument, not a condition as expressed by AuxInt. // Convert the condition to a CR bit argument by the following conversion: // // AuxInt&3 ? arg0 : arg1 for conditions LT, GT, EQ, SO
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/phiopt.go
return } switch a0.Op { case OpConst8, OpConst16, OpConst32, OpConst64: default: return } negate := false switch { case a0.AuxInt == 0 && a1.AuxInt == 1: negate = true case a0.AuxInt == 1 && a1.AuxInt == 0: default: return } if reverse == 1 { negate = !negate } a := b0.Controls[0] if negate {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 11 16:34:30 UTC 2022 - 8.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops. {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"}, // arg0 - arg1 {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"}, // arg0 - auxInt {name: "MULV", argLength: 2, reg: gp21, asm: "MULV", commutative: true, typ: "Int64"}, // arg0 * arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "Int64"}, // arg0 << auxInt, 0 <= auxInt < 64, 64 bit width {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "Int64"}, // arg0 << auxInt, 0 <= auxInt < 32, 32 bit width {name: "ROTLconst", argLength: 1, reg: gp11, asm: "ROTL", aux: "Int64"}, // arg0 rotate left by auxInt bits
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/s390x/ssa.go
p.From.Reg = r1 p.Reg = r2 p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() case ssa.OpS390XFIDBR: switch v.AuxInt { case 0, 1, 3, 4, 5, 6, 7: opregregimm(s, v.Op.Asm(), v.Reg(), v.Args[0].Reg(), v.AuxInt) default: v.Fatalf("invalid FIDBR mask: %v", v.AuxInt) } case ssa.OpS390XCPSDR: p := opregreg(s, v.Op.Asm(), v.Reg(), v.Args[1].Reg()) p.Reg = v.Args[0].Reg()
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 01:26:58 UTC 2023 - 27.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/loopbce.go
v := limit.AuxInt if !inclusive { if v == minSignedValue(limit.Type) { return false // < minint is never satisfiable. } v-- } if init.isGenericIntConst() { // Use stride to compute a better lower limit. if init.AuxInt > v { return false } v = addU(init.AuxInt, diff(v, init.AuxInt)/uint64(step)*uint64(step)) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 07 17:37:47 UTC 2023 - 11.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritedec64.go
for { off := auxIntToInt32(v.AuxInt) n := auxToSym(v.Aux) if !(is64BitInt(v.Type) && !config.BigEndian && v.Type.IsSigned() && !(b.Func.pass.name == "decompose builtin")) { break } v.reset(OpInt64Make) v0 := b.NewValue0(v.Pos, OpArg, typ.Int32) v0.AuxInt = int32ToAuxInt(off + 4) v0.Aux = symToAux(n) v1 := b.NewValue0(v.Pos, OpArg, typ.UInt32) v1.AuxInt = int32ToAuxInt(off) v1.Aux = symToAux(n)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 65.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/addressingmodes.go
} if !isInImmediateRange(v.AuxInt + p.AuxInt) { continue } if p.Aux != nil { v.Aux = p.Aux } v.AuxInt += p.AuxInt case [2]auxType{auxSymValAndOff, auxInt32}: vo := ValAndOff(v.AuxInt) if !vo.canAdd64(p.AuxInt) { continue } v.AuxInt = int64(vo.addOffset64(p.AuxInt)) case [2]auxType{auxSymValAndOff, auxSymOff}: vo := ValAndOff(v.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 26 17:19:57 UTC 2023 - 24.3K bytes - Viewed (0)