- Sort Score
- Result 10 results
- Languages All
Results 21 - 30 of 86 for vmov (0.11 sec)
-
src/cmd/internal/obj/arm64/asm7.go
{AVMOV, C_ELEM, C_NONE, C_NONE, C_ZREG, C_NONE, 73, 4, 0, 0, 0}, {AVMOV, C_ELEM, C_NONE, C_NONE, C_ELEM, C_NONE, 92, 4, 0, 0, 0}, {AVMOV, C_ELEM, C_NONE, C_NONE, C_VREG, C_NONE, 80, 4, 0, 0, 0}, {AVMOV, C_ZREG, C_NONE, C_NONE, C_ARNG, C_NONE, 82, 4, 0, 0, 0}, {AVMOV, C_ZREG, C_NONE, C_NONE, C_ELEM, C_NONE, 78, 4, 0, 0, 0}, {AVMOV, C_ARNG, C_NONE, C_NONE, C_ARNG, C_NONE, 83, 4, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
VMOVW -104(R17), W24 // 7be68e22 VMOVD (R3), W2 // 780018a3 VMOVD 128(R23), W19 // 7810bce3 VMOVD -256(R31), W0 // 7be0f823 VMOVB W8, (R0) // 78000224 VMOVB W0, 511(R3) // 79ff1824 VMOVB W21, -512(R12) // 7a006564 VMOVH W12, (R24) // 7800c325 VMOVH W8, 110(R19) // 78379a25 VMOVH W3, -70(R12) // 7bdd60e5 VMOVW W31, (R3) // 78001fe6 VMOVW W16, 64(R20) // 7810a426
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
case 34: /* mov $con,fr ==> or/add $i,t; mov t,fr */ a := AADDU if o.a1 == C_ANDCON { a = AOR } v := c.regoff(&p.From) o1 = OP_IRR(c.opirr(a), uint32(v), obj.REG_NONE, REGTMP) o2 = OP_RRR(SP(2, 1)|(4<<21), REGTMP, obj.REG_NONE, p.To.Reg) /* mtc1 */ case 35: /* mov r,lext/auto/oreg ==> sw o(REGTMP) */ r := p.To.Reg
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(MOVHZreg y:(MOV(H|B)Zreg _)) => y // repeat (MOVHZreg y:(MOVHBRload _ _)) => y (MOVHreg y:(MOV(H|B)reg _)) => y // repeat (MOV(H|HZ)reg y:(MOV(HZ|H)reg x)) => (MOV(H|HZ)reg x) // W - there are more combinations than these (MOV(WZ|WZ|WZ|W|W|W)reg y:(MOV(WZ|HZ|BZ|W|H|B)reg _)) => y // repeat (MOVWZreg y:(MOV(H|W)BRload _ _)) => y (MOV(W|WZ)reg y:(MOV(WZ|W)reg x)) => (MOV(W|WZ)reg x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
for p := cursym.Func().Text; p != nil; p = p.Link { switch p.As { case obj.AGETCALLERPC: if cursym.Leaf() { // MOV LR, Rd p.As = AMOV p.From.Type = obj.TYPE_REG p.From.Reg = REG_LR } else { // MOV (RSP), Rd p.As = AMOV p.From.Type = obj.TYPE_MEM p.From.Reg = REG_SP } case obj.ACALL, obj.ADUFFZERO, obj.ADUFFCOPY: switch p.To.Type {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/runtime/memclr_mips64x.s
msa_large_loop: VMOVB W0, (R1) VMOVB W0, 16(R1) VMOVB W0, 32(R1) VMOVB W0, 48(R1) VMOVB W0, 64(R1) VMOVB W0, 80(R1) VMOVB W0, 96(R1) VMOVB W0, 112(R1) ADDVU $128, R1 SGTU R6, R1, R3 BNE R3, R0, msa_large_loop BEQ R5, R0, done VMOVB W0, -128(R4) VMOVB W0, -112(R4) VMOVB W0, -96(R4) VMOVB W0, -80(R4) VMOVB W0, -64(R4) VMOVB W0, -48(R4) VMOVB W0, -32(R4) VMOVB W0, -16(R4) JMP done
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// rotate by constants (ROLQ x (MOV(Q|L)const [c])) => (ROLQconst [int8(c&63)] x) (ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x) (ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x) (ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x) (RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x) (RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x) (RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
cmd/xl-storage-format-v2_test.go
// Mutate signature, non strict vMod := make([][]xlMetaV2ShallowVersion, 0, len(vers)) for i, ver := range vers { newVers := make([]xlMetaV2ShallowVersion, 0, len(ver)) for _, v := range ver { v.header.Signature = [4]byte{byte(i + 10), 0, 0, 0} newVers = append(newVers, v) } vMod = append(vMod, newVers) } merged := mergeXLV2Versions(i, false, 0, vMod...) if len(merged) == 0 {
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri Mar 08 17:50:48 UTC 2024 - 36.4K bytes - Viewed (0)