{name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD"},                              // sqrt(arg0), float64
		{name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"},                              // sqrt(arg0), float32
		{name: "FMIND", argLength: 2, reg: fp21, asm: "FMIND"},                                // min(arg0, arg1)

	//TODO VFRSQRTE V18.S2, V1.S2              // 41daa12e
	//TODO FRSQRTS F17, F7, F24                // f8fcf15e
	//TODO VFRSQRTS V14.S2, V10.S2, V24.S2     // 58fdae0e
	//TODO VFSQRT V2.D2, V21.D2                // 55f8e16e
	FSQRTS F0, F9                              // 09c0211e
	FSQRTD F14, F27                            // dbc1611e
	FSUBS F25, F23, F0                         // e03a391e
	FSUBD F11, F13, F24                        // b8396b1e

	FRES:           "fres",
	FRESCC:         "fres.",
	FRSQRTE:        "frsqrte",
	FRSQRTECC:      "frsqrte.",
	FSEL:           "fsel",
	FSELCC:         "fsel.",
	FSQRTS:         "fsqrts",
	FSQRTSCC:       "fsqrts.",
	FSUBS:          "fsubs",
	FSUBSCC:        "fsubs.",
	ICBI:           "icbi",
	LD:             "ld",
	LDARX:          "ldarx",
	LDU:            "ldu",
	LDUX:           "ldux",

	FRSQRTE F1, F2                  // fc400834
	FRSQRTECC F1, F2                // fc400835
	FSQRT F1, F2                    // fc40082c
	FSQRTCC F1, F2                  // fc40082d
	FSQRTS F1, F2                   // ec40082c
	FSQRTSCC F1, F2                 // ec40082d
	FCPSGN F1, F2                   // fc420810
	FCPSGNCC F1, F2                 // fc420811
	FCMPO F1, F2                    // fc011040

(Xor(64|32|16|8) ...) => (XOR ...)

(Neg(64|32|16|8) ...) => (NEG ...)
(Neg(64|32)F ...) => (FNEG(D|S) ...)

(Com(64|32|16|8) ...) => (NOT ...)


(Sqrt ...) => (FSQRTD ...)
(Sqrt32 ...) => (FSQRTS ...)

(Copysign ...) => (FSGNJD ...)

(Abs ...) => (FABSD ...)

(FMA ...) => (FMADDD ...)

(Min(64|32)F ...) => (LoweredFMIN(D|S) ...)
(Max(64|32)F ...) => (LoweredFMAX(D|S) ...)

(Cvt64Fto32F ...) => (FRSP ...)

(CvtBoolToUint8 ...) => (Copy ...)

(Round(32|64)F ...) => (LoweredRound(32|64)F ...)

(Sqrt ...) => (FSQRT ...)
(Sqrt32 ...) => (FSQRTS ...)
(Floor ...) => (FFLOOR ...)
(Ceil ...) => (FCEIL ...)
(Trunc ...) => (FTRUNC ...)
(Round ...) => (FROUND ...)
(Copysign x y) => (FCPSGN y x)
(Abs ...) => (FABS ...)
(FMA ...) => (FMADD ...)

(Ceil        x) => (FIDBR [6] x)
(Trunc       x) => (FIDBR [5] x)
(RoundToEven x) => (FIDBR [4] x)
(Round       x) => (FIDBR [1] x)
(FMA     x y z) => (FMADD z x y)

(Sqrt32    ...) => (FSQRTS ...)

// Atomic loads and stores.
// The SYNC instruction (fast-BCR-serialization) prevents store-load
// reordering. Other sequences of memory operations (load-load,

(Floor       ...) => (FRINTMD ...)
(Round       ...) => (FRINTAD ...)
(RoundToEven ...) => (FRINTND ...)
(Trunc       ...) => (FRINTZD ...)
(FMA       x y z) => (FMADDD z x y)

(Sqrt32 ...) => (FSQRTS ...)

(Min(64|32)F ...) => (FMIN(D|S) ...)
(Max(64|32)F ...) => (FMAX(D|S) ...)

// lowering rotates
// we do rotate detection in generic rules, if the following rules need to be changed, check generic rules first.

				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FSQRTS",
		argLen: 1,
		asm:    arm64.AFSQRTS,
		reg: regInfo{
			inputs: []inputInfo{