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Results 1 - 10 of 26 for imm5 (2.3 sec)
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src/cmd/internal/obj/arm64/asm7.go
c.checkindex(p, index2, 15) imm5 |= 1 imm5 |= index1 << 1 imm4 |= index2 case ARNG_H: c.checkindex(p, index1, 7) c.checkindex(p, index2, 7) imm5 |= 2 imm5 |= index1 << 2 imm4 |= index2 << 1 case ARNG_S: c.checkindex(p, index1, 3) c.checkindex(p, index2, 3) imm5 |= 4 imm5 |= index1 << 3 imm4 |= index2 << 2 case ARNG_D:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/decode.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 10 18:59:52 UTC 2023 - 45.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
if p.Spadj == 0 && ins.as == AADDI && ins.imm >= -(1<<12) && ins.imm < 1<<12-1 { imm0 := ins.imm / 2 imm1 := ins.imm - imm0 // ADDI $(imm/2), REG, TO // ADDI $(imm-imm/2), TO, TO ins.imm = imm0 insADDI := &instruction{as: AADDI, rd: ins.rd, rs1: ins.rd, imm: imm1} return []*instruction{ins, insADDI} } // LUI $high, TMP
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/decode.go
return ImmAlt{uint8(v), uint8(rot)} } return Imm(v>>rot | v<<(32-rot)) case arg_endian: return Endian((x >> 9) & 1) case arg_fbits: return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1)) case arg_fp_0: return Imm(0) case arg_imm24: return Imm(x & (1<<24 - 1)) case arg_imm5: return Imm((x >> 7) & (1<<5 - 1)) case arg_imm5_32:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 12.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go
op = "int3" } case CMPPS, CMPPD, CMPSD_XMM, CMPSS: imm, ok := inst.Args[2].(Imm) if ok && 0 <= imm && imm < 8 { inst.Args[2] = nil op = cmppsOps[imm] + op[3:] } case PCLMULQDQ: imm, ok := inst.Args[2].(Imm) if ok && imm&^0x11 == 0 { inst.Args[2] = nil op = pclmulqOps[(imm&0x10)>>3|(imm&1)] } case XLATB: if markLastImplicit(&inst, PrefixAddrSize) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 21.4K bytes - Viewed (0) -
src/cmd/covdata/subtractintersect.go
pkeys = append(pkeys, k) } // Remove anything from pmm not found in imm. We don't need to // go the other way (removing things from imm not found in pmm) // since we don't add anything to imm if there is no pmm entry. for _, k := range pkeys { if _, found := s.imm[k]; !found { delete(s.mm.pod.pmm, k) } } s.imm = nil }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 12 12:50:46 UTC 2022 - 5.5K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9_gtables.go
o1 |= uint32(p.To.Reg&0x1f) << 21 // T o1 |= uint32(p.From.Offset&0x1) << 17 // IX o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0xffff) << 0 // imm0 o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0 // imm1 out[1] = o1 out[0] = o0 } // xxspltiw XT,IMM32 func type_xxspltiw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 16 20:18:50 UTC 2022 - 42.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
buf.WriteString(opName) l := inst.Args[3].(Imm) if l == 0 { // L == 0 is an extended mnemonic for the same. asm := fmt.Sprintf(" %s,%s,%s", gnuArg(&inst, 0, inst.Args[0], PC), gnuArg(&inst, 1, inst.Args[1], PC), gnuArg(&inst, 2, inst.Args[2], PC)) buf.WriteString(asm) startArg = 4 } case "sync": lsc := inst.Args[0].(Imm)<<4 | inst.Args[1].(Imm) switch lsc { case 0x00:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 12.2K bytes - Viewed (0) -
src/crypto/internal/bigmod/_asm/nat_amd64_asm.go
Comment("Iteration " + strconv.Itoa(i)) hi, lo := RDX, RAX // implicit MULQ inputs and outputs MOVQ(x.Offset(i*8), lo) MULQ(y) ADDQ(z.Offset(i*8), lo) ADCQ(Imm(0), hi) ADDQ(carry, lo) ADCQ(Imm(0), hi) MOVQ(hi, carry) MOVQ(lo, z.Offset(i*8)) } Store(carry, ReturnIndex(0)) RET() Label("adx") // The ADX strategy implements the following function, where c1 and c2 are
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 22:37:58 UTC 2023 - 2.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL $4, R1, R2 // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $4, R1 // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0)