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Results 21 - 30 of 83 for lowerings (0.33 sec)
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tensorflow/compiler/mlir/quantization/stablehlo/passes/bridge/passes.td
limitations under the License. ==============================================================================*/ // Declare bridge passes that perform legalization and/or lowering. include "mlir/Pass/PassBase.td" def ConvertTFQuantOpsToMHLO : Pass<"quant-convert-tf-quant-ops-to-mhlo", "mlir::func::FuncOp"> { let summary = "Convert TF Quant ops to MHLO quantizated ops.";
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Feb 23 01:41:18 UTC 2024 - 2.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/composite_lowering_pass.cc
target.addLegalDialect<arith::ArithDialect>(); if (failed(applyPartialConversion(getOperation(), target, std::move(patterns)))) { getOperation().emitError("Composite lowering pass failed."); signalPassFailure(); } } } // namespace // Creates an instance of the pass. std::unique_ptr<OperationPass<ModuleOp>> CreateCompositeLoweringPass() {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 28 23:16:05 UTC 2024 - 3K bytes - Viewed (0) -
test/codegen/copy.go
// s390x:-".*memmove" // amd64:-".*memmove" // ppc64x:-".*memmove" // ppc64x/power8:"LXVD2X" // ppc64x/power9:"LXV",-"LXVD2X" copy(a[:], a[128:]) } // Check arch-specific memmove lowering. See issue 41662 fot details func moveArchLowering1(b []byte, x *[1]byte) { _ = b[1] // amd64:-".*memmove" // arm64:-".*memmove" // ppc64x:-".*memmove" copy(b, x[:]) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Sep 22 14:09:29 UTC 2023 - 3.1K bytes - Viewed (0) -
src/cmd/cgo/internal/test/issue18146.go
nproc = 7 } if setNproc { var rlim syscall.Rlimit if syscall.Getrlimit(nproc, &rlim) == nil { max := int(rlim.Cur) / (threads + 5) if attempts > max { t.Logf("lowering attempts from %d to %d for RLIMIT_NPROC", attempts, max) attempts = max } } } if os.Getenv("test18146") == "exec" { runtime.GOMAXPROCS(1) for n := threads; n > 0; n-- { go func() {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 23:35:32 UTC 2023 - 2.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)])) // Lowering boolean ops (AndB ...) => (ANDL ...) (OrB ...) => (ORL ...) (Not x) => (XORLconst [1] x) // Lowering pointer arithmetic (OffPtr [off] ptr) && is32Bit(off) => (ADDQconst [int32(off)] ptr) (OffPtr [off] ptr) => (ADDQ (MOVQconst [off]) ptr) // Lowering other arithmetic (Ctz64 x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/composite_lowering_patterns.td
See the License for the specific language governing permissions and limitations under the License. ==============================================================================*/ // Pattern definition file for direct lowering of mhlo composites to tflite ops. include "mlir/IR/OpBase.td" include "mlir/Dialect/Arith/IR/ArithOps.td" include "mlir/Dialect/Func/IR/FuncOps.td" include "mhlo/IR/hlo_ops.td"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jun 06 18:45:51 UTC 2024 - 4.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/api/v1/compile_mlir_util.h
// passes for backend-specific ops. // lower_to_xla_hlo: Temporary parameter to be removed in imminent update. If // true, includes legalization and MHLO lowering passes. // allow_partial_conversion: when this is true, allow operations that can't be // legalized. ABSL_DEPRECATED("Use v2/legalize_tf.h::LegalizeMlirToHlo instead.") void CreateConvertMlirToXlaHloPipeline(
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 21 17:24:39 UTC 2024 - 10.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/tf_to_corert/attributes.mlir
// RUN: tf-tfrt-opt -tf-to-tfrt %s | FileCheck %s --dump-input=fail // _output_shapes and f.* attributes are removed during tf-to-tfrt lowering. // CHECK-LABEL: func @remove_unused_attr func.func @remove_unused_attr() { // CHECK: %out_op_chain = tfrt_fallback_async.executeop.seq(%arg0) key(0) cost({{.*}}) device("/device:CPU:0") "tf.SomeOp2"()
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 08 00:18:59 UTC 2024 - 4.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/decompose_reduce_dataset.cc
/*parallel_iterations=*/10, false, /*shape_invariant=*/false); // `_lower_using_switch_merge` is the default for While ops created // in TensorFlow and allows lowering to V1 control flow for loop // parallelization. dataset_while->setAttr("_lower_using_switch_merge", builder.getBoolAttr(true)); return dataset_while; }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 14K bytes - Viewed (0) -
tensorflow/compiler/jit/xla_platform_info.cc
platform_info.device_type() == DEVICE_GPU) { // We do not need to (and cannot) build a real device compiler for GPU // if the platform ID is null. We just return a placeholder for supporting // cross platform lowering. *xla_device_compiler = new XlaDeviceCompiler(/*persistor=*/nullptr, /*compiler_client=*/nullptr); return absl::OkStatus(); }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 17:23:27 UTC 2024 - 17.4K bytes - Viewed (0)