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Results 1 - 6 of 6 for FPSR (0.68 sec)
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src/runtime/defs_darwin_arm64.go
pc uint64 // program counter cpsr uint32 // current program status register __pad uint32 } type neonstate64 struct { v [64]uint64 // actually [32]uint128 fpsr uint32 fpcr uint32 } type mcontext64 struct { es exceptionstate64 ss regs64 ns neonstate64 } type ucontext struct { uc_onstack int32 uc_sigmask uint32 uc_stack stackt
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 12 21:17:22 UTC 2024 - 4.3K bytes - Viewed (0) -
src/runtime/defs_windows_arm64.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 05 08:26:52 UTC 2023 - 3.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/sys/unix/ztypes_freebsd_arm.go
} type Sigset_t struct { Val [4]uint32 } type Reg struct { R [13]uint32 Sp uint32 Lr uint32 Pc uint32 Cpsr uint32 } type FpReg struct { Fpsr uint32 Fpr [8]FpExtendedPrecision } type FpExtendedPrecision struct { Exponent uint32 Mantissa_hi uint32 Mantissa_lo uint32 } type PtraceIoDesc struct { Op int32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 9.5K bytes - Viewed (0) -
src/runtime/mkpreempt.go
l.add2("STP", "LDP", reg, 16) } // Add flag registers. l.addSpecial( "MOVD NZCV, R0\nMOVD R0, %d(RSP)", "MOVD %d(RSP), R0\nMOVD R0, NZCV", 8) l.addSpecial( "MOVD FPSR, R0\nMOVD R0, %d(RSP)", "MOVD %d(RSP), R0\nMOVD R0, FPSR", 8) // TODO: FPCR? I don't think we'll change it, so no need to save. // Add floating point registers F0-F31. for i := 0; i < 31; i += 2 { reg := fmt.Sprintf("(F%d, F%d)", i, i+1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 15.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
MSR R25, FAR_EL1 // 196018d5 MRS FPCR, R1 // 01443bd5 MSR R27, FPCR // 1b441bd5 MRS FPSR, R5 // 25443bd5 MSR R15, FPSR // 2f441bd5 MRS ID_AA64AFR0_EL1, R19 // 930538d5 MRS ID_AA64AFR1_EL1, R24 // b80538d5 MRS ID_AA64DFR0_EL1, R21 // 150538d5
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 94.9K bytes - Viewed (0)