re(`-fmessage-length=(.+)`),
	re(`-f(no-)?modules`),
	re(`-f(no-)?objc-arc`),
	re(`-f(no-)?objc-nonfragile-abi`),
	re(`-f(no-)?objc-legacy-dispatch`),
	re(`-f(no-)?omit-frame-pointer`),
	re(`-f(no-)?openmp(-simd)?`),
	re(`-f(no-)?permissive`),
	re(`-f(no-)?(pic|PIC|pie|PIE)`),
	re(`-f(no-)?plt`),
	re(`-f(no-)?rtti`),
	re(`-f(no-)?split-stack`),
	re(`-f(no-)?stack-(.+)`),
	re(`-f(no-)?strict-aliasing`),

	REG_F15
	REG_F16
	REG_F17
	REG_F18
	REG_F19
	REG_F20
	REG_F21
	REG_F22
	REG_F23
	REG_F24
	REG_F25
	REG_F26
	REG_F27
	REG_F28
	REG_F29
	REG_F30
	REG_F31

	// SIMD
	REG_V0
	REG_V1
	REG_V2
	REG_V3
	REG_V4
	REG_V5
	REG_V6
	REG_V7
	REG_V8
	REG_V9
	REG_V10
	REG_V11
	REG_V12
	REG_V13
	REG_V14
	REG_V15
	REG_V16
	REG_V17

// powers of r that we need from the original equation.
//
// Notation:
//
//   h - accumulator
//   r - key
//   m - message
//
//   [a, b]       - SIMD register holding two 64-bit values
//   [a, b, c, d] - SIMD register holding four 32-bit values
//   xᵢ[n]        - limb n of variable x with bit width i
//
// Limbs are expressed in little endian order, so for 26-bit

</li>

<li>
<code>R0.UXTB</code>
<br>
<code>R0.UXTB&lt;&lt;imm</code>:
<code>UXTB</code>: extract an 8-bit value from the low-order bits of <code>R0</code> and zero-extend it to the size of <code>R0</code>.
<code>R0.UXTB&lt;&lt;imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits.
The <code>imm</code> value can be 0, 1, 2, 3, or 4.

	o1 |= uint32((p.RestArgs[0].Addr.Reg>>5)&0x1) << 3 // CX
	o1 |= uint32(p.RestArgs[0].Addr.Reg&0x1f) << 6     // C
	o0 |= uint32(p.RestArgs[1].Addr.Offset&0xff) << 0  // IMM
	out[1] = o1
	out[0] = o0
}

// xxgenpcvwm XT,VRB,IMM
func type_xxgenpcvwm(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) {
	o0 := GenOpcodes[p.As-AXXSETACCZ]
	o0 |= uint32((p.To.Reg>>5)&0x1) << 0               // TX

second_user_data = {
    "id": 4,
    "name": "Mary",
    "joined": "2018-11-30",
}

my_second_user: User = User(**second_user_data)
```

!!! info
    `**second_user_data` bedeutet:

			a.Index = num
		case "D":
			if !isIndex {
				return nil
			}
			a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
			a.Index = num
		default:
			return errors.New("unsupported simd register extension type: " + ext)
		}
	} else {
		return errors.New("invalid register and extension combination")
	}
	return nil
}

    avatarUrl: https://avatars.githubusercontent.com/u/3631417?u=7c8f743f1ae325dfadea7c62bbf1abd6a824fc55&v=4
    url: https://github.com/kennywakeland
  - login: simw
    avatarUrl: https://avatars.githubusercontent.com/u/6322526?v=4
    url: https://github.com/simw
  - login: koconder
    avatarUrl: https://avatars.githubusercontent.com/u/25068?u=582657b23622aaa3dfe68bd028a780f272f456fa&v=4
    url: https://github.com/koconder

	ROTRV	R16, R9		// 02094856

//	LSHW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SLL	$19, R22, R21	// 0016acc0
	SLLV	$19, R22, R21	// 0016acf8
	SRL	$31, R6, R17	// 00068fc2
	SRLV	$31, R6, R17	// 00068ffa
	SRA	$8, R8, R19	// 00089a03
	SRAV	$19, R8, R7	// 00083cfb
	ROTR	$12, R8, R3	// 00281b02
	ROTRV	$8, R22, R22	// 0036b23a

//	LSHW imm ',' rreg
//	{

	github.com/minio/colorjson v1.0.8 // indirect
	github.com/minio/filepath v1.0.0 // indirect
	github.com/minio/mc v0.0.0-20240612143403-e7c9a733c680 // indirect
	github.com/minio/md5-simd v1.1.2 // indirect
	github.com/minio/pkg/v2 v2.0.19 // indirect
	github.com/minio/websocket v1.6.0 // indirect
	github.com/mitchellh/mapstructure v1.5.0 // indirect