- Sort Score
- Result 10 results
- Languages All
Results 11 - 20 of 61 for auxint (0.39 sec)
-
src/cmd/compile/internal/ssa/op.go
auxBool // auxInt is 0/1 for false/true auxInt8 // auxInt is an 8-bit integer auxInt16 // auxInt is a 16-bit integer auxInt32 // auxInt is a 32-bit integer auxInt64 // auxInt is a 64-bit integer auxInt128 // auxInt represents a 128-bit integer. Always 0. auxUInt8 // auxInt is an 8-bit unsigned integer
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 22 15:29:10 UTC 2024 - 18.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops. {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"}, // arg0 - arg1 {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"}, // arg0 - auxInt {name: "MULV", argLength: 2, reg: gp21, asm: "MULV", commutative: true, typ: "Int64"}, // arg0 * arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/addressingmodes.go
} if !isInImmediateRange(v.AuxInt + p.AuxInt) { continue } if p.Aux != nil { v.Aux = p.Aux } v.AuxInt += p.AuxInt case [2]auxType{auxSymValAndOff, auxInt32}: vo := ValAndOff(v.AuxInt) if !vo.canAdd64(p.AuxInt) { continue } v.AuxInt = int64(vo.addOffset64(p.AuxInt)) case [2]auxType{auxSymValAndOff, auxSymOff}: vo := ValAndOff(v.AuxInt)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 26 17:19:57 UTC 2023 - 24.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "Int64"}, // arg0 << auxInt, 0 <= auxInt < 64, 64 bit width {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "Int64"}, // arg0 << auxInt, 0 <= auxInt < 32, 32 bit width {name: "ROTLconst", argLength: 1, reg: gp11, asm: "ROTL", aux: "Int64"}, // arg0 rotate left by auxInt bits
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/loopbce.go
v := limit.AuxInt if !inclusive { if v == maxSignedValue(limit.Type) { return false // > maxint is never satisfiable. } v++ } if init.isGenericIntConst() { // Use stride to compute a better lower limit. if init.AuxInt < v { return false } v = subU(init.AuxInt, diff(init.AuxInt, v)/uint64(-step)*uint64(-step)) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 07 17:37:47 UTC 2023 - 11.8K bytes - Viewed (0) -
src/cmd/compile/internal/s390x/ssa.go
p.From.Reg = r1 p.Reg = r2 p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() case ssa.OpS390XFIDBR: switch v.AuxInt { case 0, 1, 3, 4, 5, 6, 7: opregregimm(s, v.Op.Asm(), v.Reg(), v.Args[0].Reg(), v.AuxInt) default: v.Fatalf("invalid FIDBR mask: %v", v.AuxInt) } case ssa.OpS390XCPSDR: p := opregreg(s, v.Op.Asm(), v.Reg(), v.Args[1].Reg()) p.Reg = v.Args[0].Reg()
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 01:26:58 UTC 2023 - 27.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/rulegen.go
default: log.Fatalf("too many controls: %d", outdata.controls) } if auxint != "" { // Make sure auxint value has the right type. rr.add(stmtf("b.AuxInt = %sToAuxInt(%s)", unTitle(outdata.auxIntType()), auxint)) } if aux != "" { // Make sure aux value has the right type. rr.add(stmtf("b.Aux = %sToAux(%s)", unTitle(outdata.auxType()), aux)) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Sep 02 22:09:21 UTC 2023 - 48.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64latelower.go
// match: (ADDSconstflags [c] x) // cond: !isARM64addcon(c) // result: (ADDSflags x (MOVDconst [c])) for { c := auxIntToInt64(v.AuxInt) x := v_0 if !(!isARM64addcon(c)) { break } v.reset(OpARM64ADDSflags) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(c) v.AddArg2(x, v0) return true } return false }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 19.3K bytes - Viewed (0)