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Results 1 - 2 of 2 for FLTD (0.36 sec)
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src/math/floor_riscv64.s
BNEZ X6, 3(PC); \ /* return NaN if x is NaN */; \ MOVD F0, ret+8(FP); \ RET; \ MOV $PosInf, X6; \ FMVDX X6, F1; \ FABSD F0, F2; \ /* if abs(x) > +Inf, return Inf instead of round(x) */; \ FLTD F1, F2, X6; \ /* Inf should keep same signed with x then return */; \ BEQZ X6, 3(PC); \ FCVTLD.MODE F0, X6; \ FCVTDL X6, F1; \ /* rounding will drop signed bit in RISCV, restore it */; \ FSGNJD F0, F1, F0; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 23 08:34:12 UTC 2024 - 1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
"FCVTLD", "FCVTDW", "FCVTDL", "FCVTWUD", "FCVTLUD", "FCVTDWU", "FCVTDLU", "FCVTSD", "FCVTDS", "FSGNJD", "FSGNJND", "FSGNJXD", "FMVXD", "FMVDX", "FEQD", "FLTD", "FLED", "FCLASSD", "FLQ", "FSQ", "FADDQ", "FSUBQ", "FMULQ", "FDIVQ", "FMINQ", "FMAXQ", "FSQRTQ", "FMADDQ", "FMSUBQ", "FNMADDQ", "FNMSUBQ", "FCVTWQ",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0)