BNEZ	X6, 3(PC);	\
	/* return NaN if x is NaN */; \
	MOVD	F0, ret+8(FP); 	\
	RET;			\
	MOV	$PosInf, X6;	\
	FMVDX	X6, F1;		\
	FABSD	F0, F2;		\
	/* if abs(x) > +Inf, return Inf instead of round(x) */; \
	FLTD	F1, F2, X6;	\
	/* Inf should keep same signed with x then return */;	\
	BEQZ	X6, 3(PC); \
	FCVTLD.MODE	F0, X6;	\
	FCVTDL	X6, F1;		\
	/* rounding will drop signed bit in RISCV, restore it */; \
	FSGNJD	F0, F1, F0;	\

	"FCVTLD",
	"FCVTDW",
	"FCVTDL",
	"FCVTWUD",
	"FCVTLUD",
	"FCVTDWU",
	"FCVTDLU",
	"FCVTSD",
	"FCVTDS",
	"FSGNJD",
	"FSGNJND",
	"FSGNJXD",
	"FMVXD",
	"FMVDX",
	"FEQD",
	"FLTD",
	"FLED",
	"FCLASSD",
	"FLQ",
	"FSQ",
	"FADDQ",
	"FSUBQ",
	"FMULQ",
	"FDIVQ",
	"FMINQ",
	"FMAXQ",
	"FSQRTQ",
	"FMADDQ",
	"FMSUBQ",
	"FNMADDQ",
	"FNMSUBQ",
	"FCVTWQ",

		{name: "FNED", argLength: 2, reg: fp2gp, asm: "FNED", commutative: true},                                                            // arg0 != arg1
		{name: "FLTD", argLength: 2, reg: fp2gp, asm: "FLTD"},                                                                               // arg0 < arg1

	FNEGS	F0, F1					// d3100020
	FNES	F0, F1, X7				// d3a300a093c31300

	// D extension
	FABSD	F0, F1					// d3200022
	FNEGD	F0, F1					// d3100022
	FNED	F0, F1, X5				// d3a200a293c21200
	FLTD	F0, F1, X5				// d39200a2
	FLED	F0, F1, X5				// d38200a2
	FEQD	F0, F1, X5				// d3a200a2

(MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVDstorezero [off] {sym} ptr mem)

// Boolean ops are already extended.
(MOVBUreg x:((FLES|FLTS|FEQS|FNES) _ _)) => x
(MOVBUreg x:((FLED|FLTD|FEQD|FNED) _ _)) => x
(MOVBUreg x:((SEQZ|SNEZ) _)) => x
(MOVBUreg x:((SLT|SLTU) _ _)) => x

// Avoid extending when already sufficiently masked.
(MOVBreg  x:(ANDI [c] y)) && c >= 0 && int64(int8(c)) == c => x

	}
	// match: (MOVBUreg x:(FLED _ _))
	// result: x
	for {
		x := v_0
		if x.Op != OpRISCV64FLED {
			break
		}
		v.copyOf(x)
		return true
	}
	// match: (MOVBUreg x:(FLTD _ _))
	// result: x
	for {
		x := v_0
		if x.Op != OpRISCV64FLTD {
			break
		}
		v.copyOf(x)
		return true
	}
	// match: (MOVBUreg x:(FEQD _ _))
	// result: x
	for {

			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "FLTD",
		argLen: 2,
		asm:    riscv.AFLTD,
		reg: regInfo{
			inputs: []inputInfo{