"VMRGEW",
	"VMRGOW",
	"VCLZLSBB",
	"VCTZLSBB",
	"LXV",
	"LXVL",
	"LXVLL",
	"LXVD2X",
	"LXVW4X",
	"LXVH8X",
	"LXVB16X",
	"LXVX",
	"LXVDSX",
	"STXV",
	"STXVL",
	"STXVLL",
	"STXVD2X",
	"STXVW4X",
	"STXVH8X",
	"STXVB16X",
	"STXVX",
	"LXSDX",
	"STXSDX",
	"LXSIWAX",
	"LXSIWZX",
	"STXSIWX",
	"MFVSRD",
	"MFFPRD",
	"MFVRD",
	"MFVSRWZ",

		return "MOV" + op[2:len(op)-1] + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"

	case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"

	case STXVX, STXVD2X, STXVW4X, STXVH8X, STXVB16X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"

	case STXV:

	LXSDX (R3)(R0), VS1             // 7c201c98
	LXSDX (R3), VS1                 // 7c201c98
	STXVD2X VS1, (R3)(R4)           // 7c241f98
	STXVD2X VS1, (R3)(R0)           // 7c201f98
	STXVD2X VS1, (R3)               // 7c201f98
	STXVW4X VS1, (R3)(R4)           // 7c241f18
	STXVW4X VS1, (R3)(R0)           // 7c201f18
	STXVW4X VS1, (R3)               // 7c201f18
	STXV VS1,16(R3)                 // f4230015

	SETBC:          "setbc",
	SETBCR:         "setbcr",
	SETNBC:         "setnbc",
	SETNBCR:        "setnbcr",
	STXVP:          "stxvp",
	STXVPX:         "stxvpx",
	STXVRBX:        "stxvrbx",
	STXVRDX:        "stxvrdx",
	STXVRHX:        "stxvrhx",
	STXVRWX:        "stxvrwx",
	VCFUGED:        "vcfuged",
	VCLRLB:         "vclrlb",
	VCLRRB:         "vclrrb",
	VCLZDM:         "vclzdm",
	VCMPEQUQ:       "vcmpequq",

		case ALXVD2X: /* lxvd2x, lxvdsx, lxvw4x, lxvh8x, lxvb16x */
			opset(ALXVDSX, r0)
			opset(ALXVW4X, r0)
			opset(ALXVH8X, r0)
			opset(ALXVB16X, r0)

		case ALXV: /* lxv */
			opset(ALXV, r0)

		case ALXVL: /* lxvl, lxvll, lxvx */
			opset(ALXVLL, r0)
			opset(ALXVX, r0)

		case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */
			opset(ASTXVW4X, r0)

	SETNBCR CR6SO, R2                       // 7c5b03c0
	STXVP VS6, 12352(R5)                    // 18c53041
	STXVPX VS22, (R1)(R2)                   // 7ec20b9a
	STXVRBX VS2, (R1)(R2)                   // 7c42091a
	STXVRDX VS2, (R1)(R2)                   // 7c4209da
	STXVRHX VS2, (R1)(R2)                   // 7c42095a
	STXVRWX VS2, (R1)(R2)                   // 7c42099a
	VCFUGED V1, V2, V3                      // 1061154d

	LXVW4X (INP)(R9), VS61
	LXVW4X (INP)(R10), VS62

	VXOR V27, V0, V27
	VXOR V28, V4, V28
	VXOR V29, V8, V29
	VXOR V30, V12, V30

	STXVW4X VS59, (OUT)(R0)
	STXVW4X VS60, (OUT)(R8)
	ADD     $64, INP
	STXVW4X VS61, (OUT)(R9)
	ADD     $-64, LEN
	STXVW4X VS62, (OUT)(R10)
	ADD     $64, OUT
	BEQ     done_vsx

	VADDUWM V1, V16, V0
	VADDUWM V5, V17, V4
	VADDUWM V9, V18, V8
	VADDUWM V13, V19, V12

forward64:
	LXVD2X	(R0)(SRC), VS32		// load 64 bytes
	LXVD2X	(IDX16)(SRC), VS33
	LXVD2X	(IDX32)(SRC), VS34
	LXVD2X	(IDX48)(SRC), VS35
	ADD	$64, SRC
	STXVD2X	VS32, (R0)(TGT)		// store 64 bytes
	STXVD2X	VS33, (IDX16)(TGT)
	STXVD2X	VS34, (IDX32)(TGT)
	STXVD2X VS35, (IDX48)(TGT)
	ADD	$64,TGT			// bump up for next set
	BC	16, 0, forward64	// continue
	ANDCC	$7, DWORDS		// remaining doublewords
	BEQ	checkbytes		// only bytes remain

	VXOR	IN0, KEY, IN0                    // vxor 1,1,3
	STXVD2X	IN0, (R0+OUTENC)
	STXVD2X	IN0, (R0+OUTDEC)

	RET

l192:
	LXSDX	(INP+R0), IN1                    // Load next 8 bytes into upper half of VSR.
	XXBRD_ON_LE(IN1, IN1)                    // and convert to BE ordering on LE hosts.
	MOVD	$4, CNT                          // li 7,4
	STXVD2X	IN0, (R0+OUTENC)
	STXVD2X	IN0, (R0+OUTDEC)
	ADD	$16, OUTENC, OUTENC

	LXVD2X	(R5)(R10), VS35
	LXVD2X	(R5)(R14), VS37
	LXVD2X	(R5)(R15), VS39
	XXLXOR	VS32, VS33, VS32
	XXLXOR	VS34, VS35, VS34
	XXLXOR	VS36, VS37, VS36
	XXLXOR	VS38, VS39, VS38
	STXVD2X	VS32, (R3)(R8)
	STXVD2X	VS34, (R3)(R10)
	STXVD2X	VS36, (R3)(R14)
	STXVD2X	VS38, (R3)(R15)
	ADD	$64, R8
	ADD	$64, R10
	ADD	$64, R14
	ADD	$64, R15
	BDNZ	loop64
	BC	12,2,LR		// BEQLR
	MOVD	R9, R6
	CMP	R6, $8
	BLE	small