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src/cmd/asm/internal/asm/testdata/arm64.s
LDPSW 8(R1), (ZR, R2) // 3f084169 STP (R3, R4), (R5) // a31000a9 STP (R3, R4), 8(R5) // a39000a9 STP.W (R3, R4), 8(R5) // a39080a9 STP.P (R3, R4), 8(R5) // a39080a8 STP (R3, R4), -8(R5) // a3903fa9 STP (R3, R4), -4(R5) // bb1000d1631300a9 STP (R3, R4), 11(R0) // 1b2c0091631300a9 STP (R3, R4), 1024(R0) // 1b001091631300a9 STP (R3, R4), (RSP) // e31300a9
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src/cmd/asm/internal/asm/testdata/arm64enc.s
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doc/asm.html
</li> <li> <code>(R5, R6)</code>: Register pair for <code>LDAXP</code>/<code>LDP</code>/<code>LDXP</code>/<code>STLXP</code>/<code>STP</code>/<code>STP</code>. </li> </ul> <p> Reference: <a href="/pkg/cmd/internal/obj/arm64">Go ARM64 Assembly Instructions Reference Manual</a> </p> <h3 id="ppc64">PPC64</h3> <p>
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src/cmd/asm/internal/asm/parse.go
// TODO: Consistency in the encoding would be nice here. if p.arch.InFamily(sys.ARM, sys.ARM64) { // Special form // ARM: destination register pair (R1, R2). // ARM64: register pair (R1, R2) for LDP/STP. if prefix != 0 || scale != 0 { p.errorf("illegal address mode for register pair") return } a.Type = obj.TYPE_REGREG a.Offset = int64(r2) // Nothing may follow return }
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src/cmd/asm/internal/asm/testdata/arm64error.s
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