def "maintains operation hierarchy"() {
        when:
        def op1 = ops.start("compile", null, new OperationIdentifier(1), null)
        def op2 = ops.start("resolve", null, new OperationIdentifier(2), new OperationIdentifier(1))

        then:
        op1.operationId.id == 1L
        op1.parent == null
        op2.operationId.id == 2L
        op2.parent == op1
    }

func extract_bit(value, bit uint32) uint32 {
	return (value >> bit) & 1
}

func bfxpreferred_4(sf, opc1, imms, immr uint32) bool {
	if imms < immr {
		return false
	}
	if (imms>>5 == sf) && (imms&0x1f == 0x1f) {
		return false
	}
	if immr == 0 {
		if sf == 0 && (imms == 7 || imms == 15) {
			return false
		}
		if sf == 1 && opc1 == 0 && (imms == 7 ||
			imms == 15 || imms == 31) {
			return false
		}
	}
	return true

//
// ======== IRs after TAC ========
// op1 = .... {tac.device = "CPU"}
// op2 = .... {tac.device = "GPU"}
// op3 = .... {tac.device = "GPU"}
// op4 = .... {tac.device = "CPU"}
//
// We will run a separate cost estimation for each op with each different
// hardwares.
//
// ======== IRs after cost-estimation ========
// op1 = .... {tac.device = "CPU"} {"CPU": 10, "GPU": -1.0}

    def "formats operations"() {
        given:
        def op1 = new ProgressOperation("STATUS_1", "VARIANT_CATEGORY", new OperationIdentifier(1), null)
        def op2 = new ProgressOperation(null,  null, new OperationIdentifier(2), op1)
        def op3 = new ProgressOperation("STATUS_2", "VARIANT_CATEGORY", new OperationIdentifier(3), op2)

        expect:
        statusBarFormatter.format(op3).first().text == "> STATUS_1 > STATUS_2"

		{name: "ADDshiftLLreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1<<arg2
		{name: "ADDshiftRLreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1>>arg2, unsigned shift
		{name: "ADDshiftRAreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1>>arg2, signed shift
		{name: "SUBshiftLLreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1<<arg2
		{name: "SUBshiftRLreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1>>arg2, unsigned shift

}

func OPDP3(sf uint32, op54 uint32, op31 uint32, o0 uint32) uint32 {
	return sf<<31 | op54<<29 | 0x1B<<24 | op31<<21 | o0<<15
}

func OPBcc(x uint32) uint32 {
	return 0x2A<<25 | 0<<24 | 0<<4 | x&15
}

func OPBLR(x uint32) uint32 {
	/* x=0, JMP; 1, CALL; 2, RET */
	return 0x6B<<25 | 0<<23 | x<<21 | 0x1F<<16 | 0<<10
}

  if (argc != 4) {
    for (int i = 1; i < argc; ++i) {
      fprintf(stderr, "Arg %d = %s\n", i, argv[i]);
    }
    fprintf(stderr, "Usage: %s location api_def1,api_def2 op1,op2,op3\n",
            argv[0]);
    exit(1);
  }
  for (int i = 1; i < argc; ++i) {
    fprintf(stdout, "Arg %d = %s\n", i, argv[i]);
  }
  std::vector<tensorflow::string> api_def_srcs = tensorflow::str_util::Split(

other extended opcodes to make it easier to see what type of branch is being
used.

The following is a brief description of the BC instruction and its commonly
used operands.

BC op1, op2, op3

	  op1: type of branch
	      16 -> bctr (branch on ctr)
	      12 -> bcr  (branch if cr bit is set)
	      8  -> bcr+bctr (branch on ctr and cr values)
		4  -> bcr != 0 (branch if specified cr bit is not set)

		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2)
		{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2)
		{name: "MADD", argLength: 3, reg: gp31, asm: "MADD"},       // +arg0 + (arg1 * arg2)
		{name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW"},     // +arg0 + (arg1 * arg2), 32-bit

	{f: func(a, b uint64) uint64 { op1 := int32(a); op2 := int32(b); return uint64(uint32(op1 / op2)) }, arg1: 0x1, arg2: 0xfffffffeffffffff, res: 0xffffffff, name: "div"},
	{f: func(a, b uint64) uint64 { op1 := int32(a); op2 := int32(b); return uint64(uint32(op1 * op2)) }, arg1: 0x1, arg2: 0x100000001, res: 0x1, name: "mul"},