(ADD x (SRLconst [c] y)) => (ADDshiftRL x y [c])
(ADD x (SRAconst [c] y)) => (ADDshiftRA x y [c])
(ADD x (SLL y z)) => (ADDshiftLLreg x y z)
(ADD x (SRL y z)) => (ADDshiftRLreg x y z)
(ADD x (SRA y z)) => (ADDshiftRAreg x y z)
(ADC x (SLLconst [c] y) flags) => (ADCshiftLL x y [c] flags)
(ADC x (SRLconst [c] y) flags) => (ADCshiftRL x y [c] flags)
(ADC x (SRAconst [c] y) flags) => (ADCshiftRA x y [c] flags)

		{name: "ADDshiftLLreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1<<arg2
		{name: "ADDshiftRLreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1>>arg2, unsigned shift
		{name: "ADDshiftRAreg", argLength: 3, reg: gp31, asm: "ADD"}, // arg0 + arg1>>arg2, signed shift
		{name: "SUBshiftLLreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1<<arg2

			}
			z := v_1.Args[1]
			y := v_1.Args[0]
			v.reset(OpARMADDshiftRLreg)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	// match: (ADD x (SRA y z))
	// result: (ADDshiftRAreg x y z)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != OpARMSRA {
				continue
			}
			z := v_1.Args[1]
			y := v_1.Args[0]

				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "ADDshiftRAreg",
		argLen: 3,
		asm:    arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14