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Results 1 - 7 of 7 for mov (0.12 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	MOV	$1234, 8(SP)			// ERROR "constant load must target register"
    	MOV	$0, 0(SP)			// ERROR "constant load must target register"
    	MOV	$0, 8(SP)			// ERROR "constant load must target register"
    	MOV	$1234, 0(SP)			// ERROR "constant load must target register"
    	MOV	$1234, 8(SP)			// ERROR "constant load must target register"
    	MOVB	$1, X5				// ERROR "unsupported constant load"
    	MOVH	$1, X5				// ERROR "unsupported constant load"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Sun Apr 07 03:32:27 GMT 2024
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  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	WORD	$0x9abcdef0	// WORD $2596069104	// f0debc9a
    
    	// MOV pseudo-instructions
    	MOV	X5, X6					// 13830200
    	MOV	$2047, X5				// 9302f07f
    	MOV	$-2048, X5				// 93020080
    	MOV	$2048, X5				// b71200009b820280
    	MOV	$-2049, X5				// b7f2ffff9b82f27f
    	MOV	$4096, X5				// b7120000
    	MOV	$2147479552, X5				// b7f2ff7f
    	MOV	$2147483647, X5				// b70200809b82f2ff
    	MOV	$-2147483647, X5			// b70200809b821200
    
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Mar 22 04:42:21 GMT 2024
    - 16.7K bytes
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  3. src/cmd/asm/internal/asm/testdata/amd64error.s

    	CALL (AX)(PC*1)                 // ERROR "invalid instruction"
    	CALL (AX)(SB*1)                 // ERROR "invalid instruction"
    	CALL (AX)(FP*1)                 // ERROR "invalid instruction"
    	// Forbid memory operands for MOV CR/DR. See #24981.
    	MOVQ CR0, (AX)                  // ERROR "invalid instruction"
    	MOVQ CR2, (AX)                  // ERROR "invalid instruction"
    	MOVQ CR3, (AX)                  // ERROR "invalid instruction"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Jun 14 00:03:57 GMT 2023
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  4. src/cmd/asm/internal/asm/testdata/386enc.s

    	MOVL 2147483648(AX), AX  // 8b8000000080
    	MOVL -2147483648(AX), AX // 8b8000000080
    	ADDL 2147483648(AX), AX  // 038000000080
    	ADDL -2147483648(AX), AX // 038000000080
    	// Make sure MOV CR/DR continues to work after changing its movtabs.
    	MOVL CR0, AX // 0f20c0
    	MOVL CR0, DX // 0f20c2
    	MOVL CR4, DI // 0f20e7
    	MOVL AX, CR0 // 0f22c0
    	MOVL DX, CR0 // 0f22c2
    	MOVL DI, CR4 // 0f22e7
    	MOVL DR0, AX // 0f21c0
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 11 18:32:50 GMT 2023
    - 1.2K bytes
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  5. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	VPERMPD $216, Y7, Y7 // c4e3fd01ffd8
    	// Check that LEAL is permitted to use overflowing offset.
    	LEAL 2400959708(BP)(R10*1), BP // 428dac15dcbc1b8f
    	LEAL 3395469782(AX)(R10*1), AX // 428d8410d6c162ca
    	// Make sure MOV CR/DR continues to work after changing its movtabs.
    	MOVQ CR0, AX // 0f20c0
    	MOVQ CR0, DX // 0f20c2
    	MOVQ CR4, DI // 0f20e7
    	MOVQ AX, CR0 // 0f22c0
    	MOVQ DX, CR0 // 0f22c2
    	MOVQ DI, CR4 // 0f22e7
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 11 18:32:50 GMT 2023
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  6. doc/asm.html

    Instead, the compiler operates on a kind of semi-abstract instruction set,
    and instruction selection occurs partly after code generation.
    The assembler works on the semi-abstract form, so
    when you see an instruction like <code>MOV</code>
    what the toolchain actually generates for that operation might
    not be a move instruction at all, perhaps a clear or load.
    Or it might correspond exactly to the machine instruction with that name.
    HTML
    - Registered: Tue May 07 11:14:38 GMT 2024
    - Last Modified: Tue Nov 28 19:15:27 GMT 2023
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  7. src/cmd/asm/internal/asm/testdata/arm64.s

    	VMOVQ	$0x8040201008040202, $0x7040201008040201, V20         // VMOVQ	$-9205322385119247870, $8088500183983456769, V20
    
    // mov(to/from sp)
    	MOVD	$0x1002(RSP), R1              // MOVD	$4098(RSP), R1              // e107409121080091
    	MOVD	$0x1708(RSP), RSP             // MOVD	$5896(RSP), RSP             // ff074091ff231c91
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
    - 94.9K bytes
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