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Results 1 - 10 of 25 for lxvrhx (0.24 sec)
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src/cmd/asm/internal/asm/testdata/ppc64_p10.s
LXVKQ $0, VS33 // f03f02d1 LXVP 12352(R5), VS6 // 18c53040 LXVPX (R1)(R2), VS4 // 7c820a9a LXVRBX (R1)(R2), VS4 // 7c82081a LXVRDX (R1)(R2), VS4 // 7c8208da LXVRHX (R1)(R2), VS4 // 7c82085a LXVRWX (R1)(R2), VS4 // 7c82089a MTVSRBM R1, V1 // 10300e42
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 14.3K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9_gtables.go
"VCLRRB", "VCLRLB", "VCFUGED", "STXVRWX", "STXVRHX", "STXVRDX", "STXVRBX", "STXVPX", "STXVP", "SETNBCR", "SETNBC", "SETBCR", "SETBC", "PEXTD", "PDEPD", "MTVSRWM", "MTVSRQM", "MTVSRHM", "MTVSRDM", "MTVSRBMI", "MTVSRBM", "LXVRWX", "LXVRHX", "LXVRDX", "LXVRBX", "LXVPX", "LXVP", "LXVKQ", "DCTFIXQQ", "DCFFIXQQ",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 16 20:18:50 UTC 2022 - 42.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 334.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
if args[1] == "0" { return op + " (" + args[2] + ")," + args[0] } return op + " (" + args[2] + ")(" + args[1] + ")," + args[0] case LXVX, LXVD2X, LXVW4X, LXVH8X, LXVB16X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX: return op + " (" + args[2] + ")(" + args[1] + ")," + args[0] case LXV: return op + " " + args[1] + "," + args[0] case LXVL, LXVLL:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
VSHASIGMAD $2, $15, V1, V2 // 104196c2 LXVD2X (R3)(R4), VS1 // 7c241e98 LXVD2X (R3)(R0), VS1 // 7c201e98 LXVD2X (R3), VS1 // 7c201e98 LXVDSX (R3)(R4), VS1 // 7c241a98 LXVDSX (R3)(R0), VS1 // 7c201a98 LXVDSX (R3), VS1 // 7c201a98 LXVH8X (R3)(R4), VS1 // 7c241e58 LXVH8X (R3)(R0), VS1 // 7c201e58
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
// cond is R1 + 24 (cond offset) + 32 LXVDSX (R1)(R21), SEL VSPLTISB $0, ZER // SEL controls whether to store a or b VCMPEQUD SEL, ZER, SEL LXVD2X (P1ptr+R0), X1H LXVD2X (P1ptr+R16), X1L LXVD2X (P1ptr+R17), Y1H LXVD2X (P1ptr+R18), Y1L LXVD2X (P1ptr+R19), Z1H LXVD2X (P1ptr+R20), Z1L LXVD2X (P2ptr+R0), X2H LXVD2X (P2ptr+R16), X2L LXVD2X (P2ptr+R17), Y2H LXVD2X (P2ptr+R18), Y2L
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0) -
src/crypto/sha256/sha256block_ppc64x.s
MOVD $·kcon(SB), TBL_STRT MOVD $0x10, R_x010 #ifdef GOARCH_ppc64le MOVWZ $8, TEMP LVSL (TEMP)(R0), LEMASK VSPLTISB $0x0F, KI VXOR KI, LEMASK, LEMASK #endif LXVW4X (CTX)(R_x000), V0 LXVW4X (CTX)(R_x010), V4 // unpack the input values into vector registers VSLDOI $4, V0, V0, V1 VSLDOI $8, V0, V0, V2 VSLDOI $12, V0, V0, V3 VSLDOI $4, V4, V4, V5 VSLDOI $8, V4, V4, V6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 14.4K bytes - Viewed (0) -
src/cmd/internal/notsha256/sha256block_ppc64x.s
MOVD $·kcon(SB), TBL_STRT MOVD $0x10, R_x010 #ifdef GOARCH_ppc64le MOVWZ $8, TEMP LVSL (TEMP)(R0), LEMASK VSPLTISB $0x0F, KI VXOR KI, LEMASK, LEMASK #endif LXVW4X (CTX)(R_x000), V0 LXVW4X (CTX)(R_x010), V4 // unpack the input values into vector registers VSLDOI $4, V0, V0, V1 VSLDOI $8, V0, V0, V2 VSLDOI $12, V0, V0, V3 VSLDOI $4, V4, V4, V5 VSLDOI $8, V4, V4, V6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 14.5K bytes - Viewed (0) -
src/internal/bytealg/compare_ppc64x.s
LXVD2X (R5)(R9),V3 LXVD2X (R6)(R9),V4 VCMPEQUDCC V3,V4,V1 BGE CR6,different RET PCALIGN $16 cmp32: // 32 - 63B ANDCC $31,R9,R9 LXVD2X (R0)(R5),V3 LXVD2X (R0)(R6),V4 VCMPEQUDCC V3,V4,V1 BGE CR6,different LXVD2X (R10)(R5),V3 LXVD2X (R10)(R6),V4 VCMPEQUDCC V3,V4,V1 BGE CR6,different BC $12,2,LR // beqlr ADD R9,R10,R10 LXVD2X (R9)(R5),V3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 28 17:33:20 UTC 2023 - 6.7K bytes - Viewed (0)