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src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VADDPD (AX), Z1, K1, Z1 // 62f1f5495808 VADDPD 8(R10), Z10, K4, Z10 // 6251ad4c589208000000 VADDPD (R10)(AX*4), Z20, K7, Z20 // 62c1dd47582482 // EVEX gather (also tests Z as VSIB index). VPGATHERDD 360(AX)(X2*4), K1, X1 // 62f27d09904c905a VPGATHERDD 640(BP)(X15*8), K3, X14 // 62327d0b90b4fd80020000 VPGATHERDD 960(R10)(X25*2), K7, X24 // 62027d0790844ac0030000
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src/cmd/asm/internal/asm/testdata/ppc64.s
// This contains the majority of valid opcode combinations // available in cmd/internal/obj/ppc64/asm9.go with // their valid instruction encodings. #include "../../../../../runtime/textflag.h" // In case of index mode instructions, usage of // (Rx)(R0) is equivalent to (Rx+R0) // In case of base+displacement mode instructions if // the offset is 0, usage of (Rx) is equivalent to 0(Rx) TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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src/cmd/asm/internal/asm/testdata/arm64.s
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 37.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
// AVX512GATHER index/index #UD cases. VPGATHERQQ (BP)(X2*2), K1, X2 // ERROR "index and destination registers should be distinct" VPGATHERQQ (BP)(Y15*2), K1, Y15 // ERROR "index and destination registers should be distinct" VPGATHERQQ (BP)(Z20*2), K1, Z20 // ERROR "index and destination registers should be distinct" VPGATHERDQ (BP)(X2*2), K1, X2 // ERROR "index and destination registers should be distinct"
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src/cmd/asm/internal/asm/testdata/amd64.s
// Intel pseudonyms for our own renamings. PADDD M2, M1 // PADDL M2, M1 MOVDQ2Q X1, M1 // MOVQ X1, M1 MOVNTDQ X1, (AX) // MOVNTO X1, (AX) MOVOA (AX), X1 // MOVO (AX), X1 // Tests for SP indexed addresses. MOVQ foo(SP)(AX*1), BX // 488b1c04 MOVQ foo+32(SP)(CX*2), DX // 488b544c20 MOVQ foo+32323(SP)(R8*4), R9 // 4e8b8c84437e0000 MOVL foo(SP)(SI*8), DI // 8b3cf4 MOVL foo+32(SP)(R10*1), R11 // 468b5c1420
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