{0x0fef0070, 0x01a00040, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}},                     // ASR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4

	// LDP <Xt>, <Xt2>, [<Xn|SP>], #<imm_3>
	{0xffc00000, 0xa8c00000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_8_signed}, nil},
	// LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm_1>}]!
	{0xffc00000, 0x29c00000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_wb_imm7_4_signed}, nil},
	// LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_3>}]!

// xxsetaccz AT
func type_xxsetaccz(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) {
	o0 := GenOpcodes[p.As-AXXSETACCZ]
	o0 |= uint32(p.To.Reg&0x7) << 23 // AT
	out[0] = o0
}

// xxsplti32dx XT,IX,IMM32
func type_xxsplti32dx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) {
	o0 := GenPfxOpcodes[p.As-AXXSPLTIW]
	o1 := GenOpcodes[p.As-AXXSETACCZ]
	o1 |= uint32((p.To.Reg>>5)&0x1) << 16                     // TX

	xArgEAX          // arg EAX
	xArgEDX          // arg EDX
	xArgES           // arg ES
	xArgFS           // arg FS
	xArgGS           // arg GS
	xArgImm16        // arg imm16
	xArgImm32        // arg imm32
	xArgImm64        // arg imm64
	xArgImm8         // arg imm8
	xArgImm8u        // arg imm8 but record as unsigned
	xArgImm16u       // arg imm8 but record as unsigned
	xArgM            // arg m

	OP_RLDCL    = 30<<26 | 8<<1 | 0<<10 | 0
	OP_EXTSWSLI = 31<<26 | 445<<2
	OP_SETB     = 31<<26 | 128<<1
)

func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
	return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
}

func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
	switch a {
	case AMOVH:

		[6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_46_46, ap_ImmUnsigned_16_31_48_63}},
	{XXSPLTIDP, 0xfff00000fc1e0000, 0x500000080040000, 0xf000000000000, // VSX Vector Splat Immediate Double-Precision 8RR:D-form (xxspltidp XT,IMM32)
		[6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}},