case arg_immediate_optional_0_65535_imm16:
		imm16 := (x >> 5) & (1<<16 - 1)
		return Imm_dcps(imm16)

	case arg_immediate_OptLSL_amount_16_0_16:
		imm16 := (x >> 5) & (1<<16 - 1)
		hw := (x >> 21) & (1<<2 - 1)
		shift := hw * 16
		if shift > 16 {
			return nil
		}
		return ImmShift{uint16(imm16), uint8(shift)}

	case arg_immediate_OptLSL_amount_16_0_48:
		imm16 := (x >> 5) & (1<<16 - 1)

//
// - arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31:
//     a W register encoded in Rm with a shift encoded in shift[23:22] and an amount
//     encoded in imm6[15:10] in the range [0,31].
//
// - arg_IAddSub:
//     An immediate for a add/sub instruction encoded in imm12[21:10] with an optional
//     left shift of 12 encoded in shift[23:22].
//
// - arg_Rt_31_1__W_0__X_1:

{"Name":"DCPS1","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"DCPS1 {#<imm>}","Code":"","Alias":""},
{"Name":"DCPS2","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"DCPS2 {#<imm>}","Code":"","Alias":""},
{"Name":"DCPS3","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"DCPS3 {#<imm>}","Code":"","Alias":""},

		{name: "ADDCconst", argLength: 1, reg: gp11xer, asm: "ADDC", typ: "(UInt64, UInt64)", aux: "Int64"},    // arg0 + imm16 -> out, CA
		{name: "SUBCconst", argLength: 1, reg: gp11xer, asm: "SUBC", typ: "(UInt64, UInt64)", aux: "Int64"},    // imm16 - arg0 -> out, CA
		{name: "ADDE", argLength: 3, reg: gp2xer1xer, asm: "ADDE", typ: "(UInt64, UInt64)", commutative: true}, // arg0 + arg1 + CA (arg2) -> out, CA

	xArgDX           // arg DX
	xArgEAX          // arg EAX
	xArgEDX          // arg EDX
	xArgES           // arg ES
	xArgFS           // arg FS
	xArgGS           // arg GS
	xArgImm16        // arg imm16
	xArgImm32        // arg imm32
	xArgImm64        // arg imm64
	xArgImm8         // arg imm8
	xArgImm8u        // arg imm8 but record as unsigned
	xArgImm16u       // arg imm8 but record as unsigned

	case arg_mem_R_pm_imm12_offset:
		// Treat [<Rn>,#+/-<imm12>] like [<Rn>{,#+/-<imm12>}]{!}
		// by forcing P=1, W=0 (index=false, wback=false).
		return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24)

	case arg_mem_R_pm_imm12_postindex:
		// Treat [<Rn>],#+/-<imm12> like [<Rn>{,#+/-<imm12>}]{!}
		// by forcing P=0, W=0 (postindex=true).
		return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21))

	{0x0ff00000, 0x03400000, 4, MOVT_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}},                         // MOVT<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12
	{0x0ff00000, 0x03000000, 4, MOVW_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}},                         // MOVW<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12

8. Move an optionally-shifted 16-bit immediate value to a register.

The instructions are MOVK(W), MOVZ(W) and MOVN(W), the assembly syntax is "op $(uimm16<<shift), <Rd>". The <uimm16>
is the 16-bit unsigned immediate, in the range 0 to 65535; For the 32-bit variant, the <shift> is 0 or 16, for the
64-bit variant, the <shift> is 0, 16, 32 or 48.

	case ABGE:
		return OPBcc(0xa)

	case ABLT:
		return OPBcc(0xb)

	case ABGT:
		return OPBcc(0xc)

	case ABLE:
		return OPBcc(0xd) /* imm19<<5 | cond */

	case AB:
		return 0<<31 | 5<<26 /* imm26 */

	case obj.ADUFFZERO, obj.ADUFFCOPY, ABL:
		return 1<<31 | 5<<26
	}

	c.ctxt.Diag("%v: bad bra %v", p, a)
	return 0
}

	o1 |= uint32(p.From.Offset&0x1) << 17                     // IX
	o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0xffff) << 0 // imm0
	o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0       // imm1
	out[1] = o1
	out[0] = o0
}

// xxspltiw XT,IMM32
func type_xxspltiw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) {
	o0 := GenPfxOpcodes[p.As-AXXSPLTIW]
	o1 := GenOpcodes[p.As-AXXSETACCZ]